F71869A
CIR PME event status.
0: CIR has no PME event.
1: CIR has a PME event to assert. Write 1 to clear to be ready for next
PME event.
4
3
2
1
0
CIR_PME_ST
ERP_PME_ST
RI2_PME_ST
RI1_PME_ST
GP_PME_ST
R/W
R/W
R/W
R/W
R/W
-
-
-
-
-
ERP PME event status.
0: ERP has no PME event.
1: ERP has a PME event to assert. Write 1 to clear to be ready for
next PME event.
RI2# PME event status.
0: RI2# has no PME event.
1: RI2# has a PME event to assert. Write 1 to clear to be ready for
next PME event.
RI1# PME event status.
0: RI1# has no PME event.
1: RI1# has a PME event to assert. Write 1 to clear to be ready for
next PME event.
GPIO PME event status.
0: GPIO has no PME event.
1: GPIO has a PME event to assert. Write 1 to clear to be ready for
next PME event.
6.11.19 Keep Last State Select Register ⎯ Index F4h
Bit
7
Name
R/W Default Description
Reserved
-
-
-
6
EN_CIRWAKEUP R/W
EN_GPWAKEUP R/W
EN_KBWAKEUP R/W
EN_MOWAKEUP R/W
0
0
0
0
Set one to enable CIR wakeup event asserted via PSOUT#.
Set one to enable GPIO wakeup event asserted via PSOUT#.
Set one to enable keyboard wakeup event asserted via PSOUT#.
Set one to enable mouse wakeup event asserted via PSOUT#.
5
4
3
The ACPI Control the PSON_N to always on or always off or keep last
state
00 : Keep last state
10 : Always on
01 : Bypass mode.
11: Always off
2-1
0
PWRCTRL
R/W
11
0
When VSB 3V comes, it will set to 1, and write 1 to clear it
VSB_PWR_LOSS R/W
6.11.20 VDDOK Delay Register ⎯ Index F5h (powered by VBAT)
Bit
Name
R/W Default
Description
The additional PWROK delay. The unit is 100 ms.
00: no delay
01: 1X
10: 2X
7-6 PWROK_DELAY R/W
0
0
11: 4X
0: RSTCON# will assert via PWROK.
1: RSTCON# will assert via PCIRST4# and PCIRST5#.
5
RSTCON_EN
R/W
138
Oct., 2011
V0.19P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
