F71869A
6.6.41 T1 OVT and High Limit Temperature Select Register ⎯ Index 64h
Bit
Name
R/W Default
R/W Reserved
Description
7-6
Reserved
0
0
0
0
Select the source temperature for T1 OVT Limit.
0: Select T1 to be compared to Temperature 1 OVT Limit.
1: Select CPU temperature from PECI to be compared to
Temperature 1 OVT Limit.
5-4 OVT_TEMP_SEL R/W
2: Select CPU temperature from AMD TSI or Intel PCH SMBus to be
compared to Temperature 1 OVT Limit.
3: Select the MAX temperature from Intel PCH SMBus to be
compared to Temperature 1 OVT Limit.
3-2
Reserved
R/W
Reserved
Select the source temperature for T1 High Limit.
0: Select T1 to be compared to Temperature 1 High Limit.
1: Select CPU temperature from PECI to be compared to
Temperature 1 High Limit.
1-0 HIGH_ TEMP_SEL R/W
2: Select CPU temperature from AMD TSI or Intel PCH SMBus to be
compared to Temperature 1 High Limit.
3: Select the MAX temperature from Intel PCH SMBus to be
compared to Temperature 1 High Limit.
6.6.42 OVT and Alert Output Enable Register 1 ⎯ Index 66h
Bit
Name
R/W Default
Description
Enable temperature 3 alert event (asserted when temperature over
7
EN_T3_ALERT
R
R
R
0
0
0
high limit)
Enable temperature 2 alert event (asserted when temperature over
6
5
EN_T2_ALERT
EN_T1_ALERT
high limit)
Enable temperature 1 alert event (asserted when temperature over
high limit)
4
3
2
1
0
Reserved
EN_T3_OVT
EN_T2_OVT
EN_T1_OVT
Reserved
R
0
0
Reserved.
R/W
R/W
R/W
R
Enable over temperature (OVT) mechanism of temperature3.
Enable over temperature (OVT) mechanism of temperature2.
Enable over temperature (OVT) mechanism of temperature1.
Reserved.
0
1
0h
82
Oct., 2011
V0.19P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
