F71869A
6.6.30 PECI Master DATA6 Register ⎯ Index 49h
Bit
Name
R/W Default
Description
For RdIAMSR() and RdPkgConfig()
“DATA[15:8]”.
,
this byte represents
7-0
PECI_DATA6
R/W
0
For WrPkgConfig(), this byte represents “DATA[23:16]”
6.6.31 PECI Master DATA7 Register ⎯ Index 4Ah
Bit
Name
R/W Default
Description
For RdIAMSR() and RdPkgConfig()
“DATA[23:16]”.
,
this byte represents
7-0
PECI_DATA7
R/W
0
For WrPkgConfig(), this byte represents “DATA[31:24]”
6.6.32 PECI Master DATA8 Register ⎯ Index 4Bh
Bit
Name
R/W Default
Description
For RdIAMSR() and RdPkgConfig()
“DATA[31:24]”.
,
this byte represents
7-0
PECI_DATA8
R/W
0
For WrPkgConfig(), this byte represents “AW FCS”
6.6.33 PECI Master DATA9 Register ⎯ Index 4Ch
Bit
Name
R/W Default
Description
For RdIAMSR(), this byte represents “DATA[39:32]”.
For WrPkgConfig(), this byte represents “Completion Code”
7-0
PECI_DATA9
R/W
0
6.6.34 PECI Master DATA10 Register ⎯ Index 4Dh
Bit
Name
R/W Default
R/W
Description
7-0
PECI_DATA10
0
For RdIAMSR(), this byte represents “DATA[47:40]”.
6.6.35 PECI Master DATA11 Register ⎯ Index 4Eh
Bit
Name
R/W Default
R/W
Description
7-0
PECI_DATA11
0
For RdIAMSR(), this byte represents “DATA[55:48]”.
6.6.36 PECI Master DATA12 Register ⎯ Index 4Fh
Bit
Name
R/W Default
R/W
Description
7-0
PECI_DATA12
0
For RdIAMSR(), this byte represents “DATA[63:56]”.
Temperature Setting
6.6.37 Temperature PME# Enable Register ⎯ Index 60h
Bit
Name
R/W Default
Description
If set this bit to 1, PME# signal will be issued when TEMP3 exceeds
OVT limit setting.
7
EN_ T3_OVT_PME R/W
EN_ T2_OVT_PME R/W
0
0
If set this bit to 1, PME# signal will be issued when TEMP2 exceeds
OVT setting.
6
79
Oct., 2011
V0.19P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
