F71869A
6.6.39 Temperature Real Time Status Register ⎯ Index 62h
Bit
Name
R/W Default
Description
Set when the TEMP3 exceeds the OVT limit. Clear when the TEMP3
is below the “OVT limit –hysteresis” temperature.
Set when the TEMP2 exceeds the OVT limit. Clear when the TEMP2
is below the “OVT limit –hysteresis” temperature.
Set when the TEMP1 exceeds the OVT limit. Clear when the TEMP1
is below the “OVT limit –hysteresis” temperature.
Reserved
7
T3_OVT
R/W
R/W
0
0
6
T2_OVT
5
4
3
T1_OVT
Reserved
T3_EXC
R/W
R/W
R/W
0
0
0
Set when the TEMP3 exceeds the high limit. Clear when the TEMP3
is below the “high limit –hysteresis” temperature.
Set when the TEMP2 exceeds the high limit. Clear when the TEMP2
is below the “high limit –hysteresis” temperature.
Set when the TEMP1 exceeds the high limit. Clear when the TEMP1
is below the “high limit –hysteresis” temperature.
Reserved
2
T2_EXC
R/W
0
1
0
T1_EXC
R/W
R/W
0
0
Reserved
6.6.40 Temperature BEEP Enable Register ⎯ Index 63h
Bit
Name
EN_T3_
R/W Default
Description
If set this bit to 1, BEEP signal will be issued when TEMP3 exceeds
7
R/W
R/W
0
0
OVT_BEEP
EN_ T2_
OVT limit setting.
If set this bit to 1, BEEP signal will be issued when TEMP2 exceeds
6
OVT_BEEP
EN_ T1_
OVT limit setting.
If set this bit to 1, BEEP signal will be issued when TEMP1 exceeds
5
4
3
R/W
R/W
R/W
0
0
0
OVT_BEEP
Reserved
EN_
OVT limit setting.
Reserved
If set this bit to 1, BEEP signal will be issued when TEMP3 exceeds
T3_EXC_BEEP
EN_
high limit setting.
If set this bit to 1, BEEP signal will be issued when TEMP2 exceeds
2
R/W
0
T2_EXC_BEEP
EN_
high limit setting.
If set this bit to 1, BEEP signal will be issued when TEMP1 exceeds
1
0
R/W
R/W
0
0
T1_EXC_BEEP
Reserved
high limit setting.
Reserved
81
Oct., 2011
V0.19P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
