F71869A
6.6.16 Voltage-Protect Shut Down Enable Register ⎯ Index 10h
Bit
7
Name
R/W Default
Description
Reserved
V6_VP_EN
V5_VP_EN
Reserved
V0_VP_EN
-
0
0
0
0
0
Reserved.
6
R/W
R/W
-
Voltage-Protect shut down enable for VIN6
Voltage-Protect enable for VIN5
Reserved
5
4-1
0
R/W
Voltage-Protect shut down enable for 3VCC
6.6.17 Voltage-Protect Status Register (Powered by VBAT) ⎯ Index 11h
Bit
Name
R/W Default
Description
7-6
Reserved
-
0
Reserved.
This bit is voltage-protect status. Once one of the monitored voltages
(3VCC, VIN5, VIN6) over its related over-voltage limits or under its
related under-voltage limits and if the related voltage-protect shut
down enable bit is set, this bit will be set to 1. Write a 1 to this bit will
clear it to 0. (This bit is powered by VBAT)
R/W
C
0
V_EXC_VP
0
6.6.18 Voltage-Protect Configuration Register (Powered by VBAT) ⎯ Index 12h
Bit
Name
R/W Default
Description
7-4
Reserved
-
-
Reserved.
PSON# de-active time select in alarm mode of voltage protection.
00: PSON# tri-state 0.5 sec and then inverted of S3# when over
voltage or under voltage occurs.
01: PSON# tri-state 1 sec and then inverted of S3# when over voltage
3-2
PU_TIME
R/W
2’h1 or under voltage occurs.
10: PSON# tri-state 2 sec and then inverted of S3# when over voltage
or under voltage occurs.
11: PSON# tri-state 4 sec and then inverted of S3# when over voltage
or under voltage occurs.
VP_EN_DELAY could set the delay time to start voltage protecting
after VDD power is ok when OVP_MODE is 1. (OVP_MODE is
strapped by RTS1# pin)
2’h2 00: bypass
01: 50ms
1-0
VP_EN_DELAY R/W
10: 100ms
11: 200ms
75
Oct., 2011
V0.19P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
