F71869A
GPIO15/LED_VSB/ALERT# function select.
{LED_VSB_EN, GPIO15_EN}
5
4
LED_VSB_EN
R/W
0
0
1x: The pin function is LED_VSB.
01: The pin function is GPIO15.
00: The pin function is ALERT#.
RSTCON# Enable Register:
0: The pin function of GPIO12/ RSTCON#/FANCTL1 is GPIO12/
FANCTL1
RSTCON_PIN_EN R/W
1: The pin function of GPIO12/RSTCON#/FANCTL1 is RSTCON#.
S0P5_Gate#/GPIO13/BEEP function select.
If S0P5_Gate#_EN is set , the ping function is S0P5_Gate#, The pin
function is determined by
{ S0P5_Gate#_EN, GPIO13_EN}
1x: The pin function is S0P5_Gate#.
01: The pin function is GPIO13.
00: The pin function is BEEP.
3
R/W
1
S0P5_Gate# _EN
2
1
FDC_GP_EN
UR2_GP_EN2
R/W
R/W
1
1
Set “1” will disable FDC and change the FDC pins to GPIOs.
= 0 set pin5, 6 to be SOUT2 and SIN2
= 1 will change pin5, 6 (SOUT2 and SIN2) to GPIOs.
Set UR2_GP_EN1 and UR2_GP_EN2 will also disable UART2 I/O
port.
= 0 will change pin 1, 2, 3, 126, 127 and 128 to be DTR2#, RTS2#,
DSR2#, DCD2#, RI2# and CTS2#.
0
UR2_GP_EN1
R/W
1
= 1 will change pin 1, 2, 3, 126, 127 and 128 to be GPIO.
Set UR2_GP_EN1 and UR2_GP_EN2 will also disable UART2 I/O
port.
6.1.14 WDT Clock Divisor Low Byte ⎯ Index 2Ah (Powered by VBAT, CLK_TUNE_EN = 1)
Bit
Name
R/W Default
Description
This is the high nibble of 12-bit divisor for WDT clock. The clock used
for WDT is 10Hz which is divided by internal 10KHz clock. Program
this divisor to fine tune clock.
7-0 WDT_CLK_DIV[7:0] R/W
E7h
60
Oct., 2011
V0.19P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
