F71869A
This is the high nibble of 12-bit count for WDT clock fine tune.
Hardware use 48MHz clock to count the internal 500KHz clock 10
times. The ideal value will be 960. The error is used to calculate the
divisor for WDT clock.
CLK_TUNE_CNT[7
:0]
7-0
R/W
-
6.1.19 Wakeup Control Register ⎯ Index 2Dh (Powered by VBAT)
Bit
Name
R/W Default
Description
0: SLOTOCC# is pull-up to VSB3V.
7
SLOT_PWR_SEL R/W
VSBOK_HYS_DIS R/W
0
0
1: SLOTOCC# is pull-up to VBAT.
Set “1” to disable VSBOK hysteresis.
6
0: VSB3V power good level is 3.05V and not good level is 2.95V.
1: VSB3V power good level is 2.8V and not good level is 2.5V.
By VSBOK_HYS_DIS and VSBOK_LVL_SEL, RSMRST# falling edge
could be determined:
VSBOK_LEVEL
R/W
5
1
_SEL
00: when VSB3V is lower than 2.95V.
01: when VSB3V is lower than 2.5V.
10: when VSB3V is lower than 3.05V.
11: when VSB3V is lower than 2.8V.
4
3
KEY_SEL_ADD R/W
0
1
This bit is added to add more wakeup key function.
0: disable keyboard/mouse wake up.
1: enable keyboard/mouse wake up.
WAKEUP_EN
R/W
63
Oct., 2011
V0.19P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
