F71869A
Set “1” to power down UART 2. The clock will stop.
2
SOFTPD_UR2
R/W
0
Set “1” to power down UART 1. The clock will stop.
Set “1” to power down FDC. The clock will stop.
1
0
SOFTPD_UR1
SOFTPD_FDC
R/W
R/W
0
0
6.1.8 UART IRQ Sharing Register ⎯ Index 26h
Bit
7
Name
R/W Default
Description
0: CLKIN is 48MHz
1: CLKIN is 24MHz
CLK24M_SEL
Reserved
R/W
-
0
-
6
Reserved.
0: The debug port address is 0x80.
5
DPORT_DEC_SEL R/W
0
1: The debug port address is UART2 base address.
4
3
Reserved
-
-
Reserved.
Set “1” to switch index 0x29 ~ 0x2C to WDT clock fine tune registers.
CLK_TUNE_EN R/W
0
0: UART transmits data immediately after writing THR.
2
1
0
TX_DEL_1BIT
IRQ_MODE
IRQ_SHAR
R/W
R/W
R/W
0
0
0
1: UART transmits data delay one bit time after writing THR.
0: PCI IRQ sharing mode (low level).
1: ISA IRQ sharing mode (low pulse).
0: disable IRQ sharing of two UART devices.
1: enable IRQ sharing of two UART devices.
6.1.9 Configuration Port Select Register ⎯ Index 27h
Bit
Name
R/W Default
Description
1: Alarm mode. Voltage protection is default disabled.
0: Force mode. Voltage protection is default enabled.
7
OVP_MODE
R/W
-
This bit is power on strapped by RTS1#/STRAP_PROTECT. Pull down
to select force mode.
Debug port output select.
6
TEMP_OUT_EN R/W
0
0: 80 port data.
1: Temperature fetched by hardware mmonitor.
56
Oct., 2011
V0.19P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
