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F71869AD 参数 Datasheet PDF下载

F71869AD图片预览
型号: F71869AD
PDF下载: 下载PDF文件 查看货源
内容描述: 超级I / O +硬件监控 [Super I/O + Hardware Monitor]
分类和应用: 监控
文件页数/大小: 156 页 / 1561 K
品牌: FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
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F71869A  
0: Disable debug port.  
1: Enable debug port.  
5
4
DPORT_EN  
R/W  
R/W  
-
-
This bit is power on strapped by  
GPIO26/SOUT2/SEGB/STRAP_DPORT. Pull down to disable.  
0: The configuration register port is 2E/2F.  
1: The configuration register port is 4E/4F.  
PORT_4E_EN  
This register is power on trapped by SOUT1/ Config4E_2E. Pull down  
to select port 2E/2F.  
3-1  
0
Reserved  
-
-
-
Reserved.  
This bit is the pin status of TIMING_GPIO pin.  
0: Disable power sequence control.  
1: Enable power sequence control.  
TIMING_EN  
R
6.1.10 Multi-Function Select Register 1Index 28h (Powered by VSB3V)  
Bit  
Name  
R/W Default  
Description  
Select GPIO5/GPIO3 reset signal.  
7
FDC_GP_RST_SEL R/W  
0
0
1
0: Reset by internal VSB3V power good.  
1: Reset by LRESET#.  
6
5
Reserved  
R/W  
R/W  
Reserved  
0: S3_Gate#/GPIO05/WDTRST# functions as GPIO05/WDTRST#  
determined by GPIO05_EN.  
PWR_  
S3_Gate#_EN  
1: S3_Gate#/GPIO05/WDTRST# functions as S3_Gate#.  
0: S3P5_Gate#/SLOTOCC#/GPIO04 functions as  
SLOTOCC#/GPIO04 determined by GPIO04_EN.  
PWR_  
4
3
R/W  
R/W  
1
1
S3P5_Gate#_EN  
1: S3P5_Gate#/SLOTOCC#/GPIO04 functions as S3P5_Gate#.  
0: S3_Gate#/GPIO05/WDTRST# functions as WDTRST if PWR_  
S3_Gate#_EN is not set.  
GPIO05_EN  
GPIO04_EN  
1: S3_Gate#/GPIO05/WDTRST# functions as GPIO05 is PWR_  
S3_Gate#_EN is not set.  
0: S3P5_Gate#/SLOTOCC#/GPIO04 functions as SLOTOCC# if  
PWR_ S3P5_Gate#_EN is not set.  
2
R/W  
0
1: S3P5_Gate#/SLOTOCC#/GPIO04 functions as GPIO04 if PWR_  
S3P5_Gate#_EN is not set.  
57  
Oct., 2011  
V0.19P  
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