F71869A
This is the high nibble of 12-bit count for WDT clock fine tune.
Hardware use 48MHz clock to count the internal 500KHz clock 10
times. The ideal value will be 960. The error is used to calculate the
divisor for WDT clock.
CLK_TUNE_CNT[1
1:8]
3-0
R/W
-
6.1.17 Multi-Function Select Register 5 ⎯ Index 2Ch (Powered by I_VSB3V, CLK_TUNE_EN = 0)
Bit
Name
R/W Default
Description
Enable pin 60 SDA function.
7
TSI_PIN60_EN R/W
TSI_PIN59_EN R/W
TSI_PIN58_EN R/W
TSI_PIN57_EN R/W
0
0
0
0
0
0
0: The pin function is GPIO11/PCI_RST5#.
1: The pin function is SDA.
Enable pin 59 SCL function.
6
5
4
3
2
0: The pin function is GPIO10/PCI_RST4#.
1: The pin function is SCL.
Enable pin 58 SDA function.
0: The pin function is PECI.
1: The pin function is SDA.
Enable pin 57 SCL function.
0: The pin function is CIR_LED#.
1: The pin function is SCL.
CIRRX#/GPIO03 function select.
0: The pin function is CIRRX#.
1: The pin function is GPIO03.
GPIO03_EN
GPIO02_EN
R/W
R/W
CIRTX#/GPIO02function select.
0: The pin function is CIRTX#.
1: The pin function is GPIO02.
CIRWB#/GPIO01 function select.
0: The pin function is CIRWB#.
1: The pin function is GPIO01.
1
0
GPIO01_EN
Reserved
R/W
R/W
0
0
Reserved
6.1.18 WDT Clock Fine Tune Count ⎯ Index 2Ch (Powered by VSB3V, CLK_TUNE_EN = 1)
Bit Name R/W Default Description
62
Oct., 2011
V0.19P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
