RC4200
PRODUCT SPECIFICATION
Divider Circuit with Offset Adjustment
+VREF
R
R
5
R
R
d
c
b
a
RAX
V Z
(Input)
R4
R1
8
VX
(Input)
+VS
+VS
VX (Offset)
I
I
1
4
R10
R11
R12
R8
R6
7
R13 ZOS
R5
RC4200
Multiplier
VZ (Offset)
XOS
R7
-VS
1
2
+VS
-VS
µ
0.1
F
I
RO
2
R21 = R
b
4
I
YOS
R18
VO
(Output)
R19
3
3
6
R20
R9
0.1µF
-VS
-VS
µ
0.1
F
R
ao
+VS
R14
R15
R16
R18-R21 can be used in place of R9 to help
cancel gain error due to resistor product
mis-match (See Appendix 1).
R17 VOS
VO (Offset)
-VS
65-1878
General
Example: Two-Quad Divider
V = K(V /V ), K = k, V = +V = +15V
10K ≤ R = R = R ≤ 50K
5
13 17
0
X
Z
REF
S
R + R ≈ R | | R | | R | | R
-10 ≤ V ≤ +10, therefore ∆V = 20
7
8
1
a
az
ao
X
X
R
6
≈ R (V /0.05)
0 ≤ V ≤ +10, therefore ∆V = 20
Z Z
7
S
R = R
-10 ≤ V ≤ +10, therefore ∆V = 20
9
b
0 0
R
10
R
11
R
12
R
14
R
16
≈ 100 x R
= 20K
= 100K
R = 26.7K
R = 333K
1
4
0
R = 60K
R , R , R = 10K
13 17
b
5
R = 50K
R , R = 1K
15
4
7
+ R ≈ R | | R
15
R = 37.5K
R , R = 20K
11
0
c
c
8
≈ R (V /0.10)
R = 300K
d
R , R , R = 300K
15
S
6
9
16
R = 187.5K
R
10
R
12
= 4.7M
= 100K
a
R
az
R
ao
= 31.25
= 133K
Figure 7. Divider Circuit with Offset Adjustment
8
REV. 1.2.1 6/14/01
FAIRCHILD [ FAIRCHILD SEMICONDUCTOR ]
