5V
0
CMP
CMP
1.6s
Shut down
0
1V
0
2V
0
OLP
-1V
OLR
BCT
VIN(V)
OUTA
-2V
VIN-7(V)
7V
32 pulses counting
Shut down
OUTB
0
V
IN(V)
Counter reset
0
0
0
OUTC
VIN-7(V)
OUTA
OUTB
7V
OUTD
0
OUTC
OUTD
Figure 51. Open-Lamp Protection in Striking Mode
5V
Figure 49. Over-Voltage Protection in Normal Mode
CMP
0
10ms
Shut down
Arc Protection: If the maximum of the rectified OLR
max
input voltages ( V ) is higher than 3V, the IC enters
0.5V
0
-0.5V
OLR
OLP
shutdown mode without delay, as shown in Figure 50.
VIN(V)
CMP
OUTA
VIN-7(V)
0
7V
OUTB
3V
0
VIN(V)
OLR
OUTC
0
VIN-7(V)
7V
OUTD
Shut down
0
OUTA
Figure 52. Open-Lamp Protection in Normal Mode
OUTB
0
Short-Lamp Protection: If the minimum of the rectified
OUTC
min
OLR voltages ( V ) is less than 0.3V in normal mode,
OLR
OUTD
0
the IC is shut down after a delay of 1ms, as shown in
Figure 53. This protection is disabled in striking mode to
ignite lamps reliably.
Figure 50. Arc Protection
Open-Lamp Protection: If the minimum of the rectified
min
OLP
OLP voltages ( V
) is less than 1V during initial
operation, the IC operates in striking mode only for 1.6s,
min
OLP
as shown in Figure 51. After ignition, if V
is less than
0.5V in normal mode, the IC is shut down after a delay of
10ms, as shown in Figure 52.
Figure 53. Short-Lamp Protection
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
18
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