Open-Lamp Regulation: When the maximum of the
2V
max
rectified OLR input voltages ( V ) is more than 2V, the
OLR
VBDIM
BCT
IC enters regulation mode and controls CMP voltage.
0.5V
0
The IC limits the lamp voltage by decreasing CMP
max
OLR
source current. If V
is between 1.8V and 2V, CMP
CMP
source current decreases from 22µA to 1µA. Then, if
0.5V
0
max
V
reaches 2V, CMP source current decreases to
OLR
Striking
mode
0µA, so CMP voltage remains constant and the lamp
1V
0
voltage also remains constant, as shown in Figure 47.
OLP
max
OLR
Finally, if V
is more than 2.2V, the error amplifier for
-1V
OLR is operating and CMP sink current increases, so
CMP voltage decreases and the lamp voltage maintains
the determined value.
VIN(V)
OUTA
VIN-7(V)
7V
max
OLR
OUTB
At the same time, while V
is more than 2V, the
0
counter starts counting 32 rectified OLR pulses in normal
mode, then the IC enters shutdown, as shown in Figure
49. This counter is reset by detecting the positive edge
of BCT. This protection is disabled in striking mode to
ignite lamps reliably.
VIN(V)
OUTC
V
IN-7(V)
7V
OUTD
0
Figure 45. Burst Dimming During Striking Mode
Output Drives: FAN7317 uses the new phase-shift
method for full-bridge Cold Cathode Fluorescent Lighting
(CCFL) drive. As a result, the temperature difference
between the left and the right leg is almost zero,
because ZVS occurs in both of the legs by turns. The
detail timing is shown in Figure 46.
Figure 47. Open-Lamp Regulation in Striking Mode
CMP
OLR
2V OLR
2.2V OLR
0
2.2V
2V
0
-2V
-2.2V
0
iCMP
Figure 46. MOSFETs Gate Drive Signal
Figure 48. Open-Lamp Regulation in Normal Mode
Protections: The FAN7317 provides the following latch-
mode protections: Open-Lamp Regulation (OLR), Arc
Protection, Open-Lamp Protection (OLP), Short-Lamp
Protection (SLP), CMP-High Protection, and Thermal
Shutdown (TSD). The latch is reset when VIN falls to the
UVLO voltage or ENA is pulled down to GND.
© 2007 Fairchild Semiconductor Corporation
FAN7317 • 1.0.2
www.fairchildsemi.com
17
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