XRT86L30
REV. 1.0.1
SINGLE T1/E1/J1 FRAMER/LIU COMBO
T
ABLE 48: RECEIVE
I
NTERFACE
C
ONTROL
R
EGISTER (RICR) - T1 MODE
EGISTER (RICR)
Register 33 - T1 Mode
R
ECEIVE
INTERFACE
C
ONTROL
R
0X0122
B
IT
F
UNCTION
TYPE
D
EFAULT
DESCRIPTION-OPERATION
4
RxFr1544
R/W
0
Clock Inversion/RxSig
1 = RxChn[0]/RxSig outputs signaling information, RxChn[1]/RxFrTD will out-
put fractional channel data in 1.544 MHz mode and RxChn[2] will output the
serial channel number of each time slot.
0 = RxChn[4:0] outputs the parallel channel number as usual.
3
2
RxICLKINV
RxMUXEN
N/A
0
0
Clock inversion
0 = Data transition happens on the rising edge of the transmit clocks.
1 = Data transition happens on the falling edge of the transmit clocks.
R/W
Mux Enable
0 = No channel Multiplexing.
1 = Four channels are multiplexed in single serial stream.
1
0
RxIMODE[1]
RxIMODE[0]
R/W
R/W
0
0
Rx Interface Mode selection
This mode selection determines the interface speed.
When RxMUXEN = 0,
00 = Receive interface is presenting data at a rate of 1.544Mbit/s.
01 = Receive interface is presenting data at a rate of 2.048Mbit/s.
10 = Receive interface is presenting data at a rate of 4.096Mbit/s.
11 = Receive interface is presenting data at a rate of 8.192Mbit/s.
When RxMUXEN = 1,
00 = Receive interface is taking data from the four LIU input channels 0
through 3 and byte-multiplexing into a 12.352MHz serial output on channel 0.
The TxSYNC pulse remains “High” during the framing bit of each DS-1 frame.
01 = Receive interface is taking data from the four LIU input channels 0
through 3 and byte-multiplexing into a 16.384MHz serial output on channel 0.
The TxSYNC pulse remains “High” during the framing bit of each DS-1 frame.
10 = Receive interface is taking data from the four LIU input channels 0
through 3 and byte-multiplexing into a 16.384MHz serial output on channel 0
(HMVIP Mode). The TxSYNC pulse remains “High” during the last two bits of
the previous DS-1 frame and the first two bits of the current DS-1 frame.
11 = Receive interface is taking data from the four LIU input channels 0
through 3 and byte-multiplexing into a 16.384MHz serial output on channel 0
(H.100 Mode). The TxSYNC pulse remains “High” during the last bit of the
previous DS-1 frame and the first bit of the current DS-1 frame.
NOTE: Channels 4 through 7 are multiplexed into the serial output at channel
4.
TABLE 49: DS1 TEST REGISTER
Register 34
DS1 Test Register (DS1TR)
0x0123
B
IT
FUNCTION
TYPE
D
EFAULT
DESCRIPTION-OPERATION
7
PRBSTyp
R/W
0
PRBS Pattern Type
15
14
0 = The (X + X +1) PBRS Polynomial is generated.
1 = QRTS (Quasi-Random Test Signal) Pattern is generated.
6
ERRORIns
R/W
0
Error Insertion
0 to 1 transition will cause one output bit inverted
68
EXAR [ EXAR CORPORATION ]
