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XRT86L30IV 参数 Datasheet PDF下载

XRT86L30IV图片预览
型号: XRT86L30IV
PDF下载: 下载PDF文件 查看货源
内容描述: 单一T1 / E1 / J1成帧器/ LIU COMBO [SINGLE T1/E1/J1 FRAMER/LIU COMBO]
分类和应用:
文件页数/大小: 284 页 / 1793 K
品牌: EXAR [ EXAR CORPORATION ]
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XRT86L30  
REV. 1.0.1  
SINGLE T1/E1/J1 FRAMER/LIU COMBO  
T
ABLE 21: TRANSMIT  
S
IGNALING AND  
D
ATA  
INK  
L
INK  
S
ELECT  
REGISTER - T1 MODE  
R
EGISTER 10 - T1 MODE  
TRANSMIT  
S
IGNALING AND ATA  
D
L
S
ELECT  
R
EGISTER (TSDLSR)  
HEX ADDRESS:0X010A  
B
IT  
F
UNCTION  
TYPE  
D
EFAULT  
DESCRIPTION-OPERATION  
5
TxDLBW[1]  
R/W  
R/W  
0
0
Data Link Bandwidth  
00 = FDL is a 4kHz data link channel  
01 = FDL is a 2kHz data link channel carried by odd framing bits  
(1,5,9....)  
4
TxDLBW[0]  
R/W  
0
10 = FDL is a 2kHz data link channel carried by even framing  
bits(3,7,11...)  
3
2
TxDE[1]  
TxDE[0]  
R/W  
R/W  
0
0
DE Select  
00 = The D/E time slots are inserted from TxSER.  
01 = The D/E time slots are inserted from the LAPD controller.  
10 = The D/E time slots are inserted from the serial signaling input.  
11 = The D/E time slots are inserted from the fractional input.  
1
0
TxDL[1]  
TxDL[0]  
R/W  
R/W  
0
0
DL Select  
00 = LAPD Controller/SLC96 Buffer. The data link bits are inserted  
from the LAPD controller. (LAPD1 is the only controller that can be  
used to transport LAPD messages through the data link bits)  
01 = Serial Input. The data link bits are inserted from serial data  
input.  
10 = Overhead Input. The data link bits are inserted from overhead  
input.  
11 = None (forced to 1). The data link bits are forced to 1.  
TABLE 22: FRAMING  
C
ONTROL  
REGISTER E1 MODE  
R
EGISTER 11 -- E1 MODE  
F
RAMING  
C
ONTROL EGISTER (FCR)  
R
H
EX  
ADDRESS: 0X010B  
B
IT UNCTION  
F
TYPE  
D
EFAULT  
DESCRIPTION-OPERATION  
7
RSYNC  
R/W  
0
Force Re-Synchronization  
A 0 to 1 transition in this bit-field forces the Receive E1 Framer to  
restart the synchronization process. This bit field is automatically  
cleared (set to 0) after frame synchronization is reached.  
6
5
CASC(1)  
CASC(0)  
R/W  
R/W  
0
0
Loss of CAS Multiframe Alignment Criteria Select  
These two Read/Write bits are used to select the Loss of CAS Multi-  
frame Alignment Declaration criteria. The relationship between the  
state of these two bit fields and the corresponding Loss of CAS Multi-  
Frame is presented below.  
00 = Two consecutive CAS Multi-Frames with Multiframe Alignment  
Signal (MAS) errors  
01 = Three consecutive CAS Multi-Frames with MAS errors  
10 = Four consecutive CAS Multi-Frames with MAS errors  
11 = Eight consecutive CAS Multi-Frames with MAS errors  
NOTE: These bits are only active if Channel Associated Signaling is  
used.  
48  
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