XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
REV. 1.0.1
TABLE 18: SYNCHRONIZATION MUX REGISTER - E1 MODE
R
EGISTER 9 - E1 MODE
IT UNCTION
S
YNCHRONIZATION MUX REGISTER (SMR)
HEX ADDRESS: 0X0109
B
F
TYPE
D
EFAULT
DESCRIPTION-OPERATION
1
CRCSRC
R/W
0
CRC-4 Bits Source Select
This Read/Write bit-field is used to configure the transmit section of
the channel to use either internal generation or the TxSER_n input
pin as the source of the CRC-4 bits inserted into the outbound
frames.
0 = Internally Generated and inserted into E1 data stream internally.
1 = Tx_SER Input: Transmit Payload data Input port will be source of
CRC-4 bits.
NOTE
:
This bit-field is ignored if CRC Multiframe Alignment is
disabled
0
FSRC
R/W
0
Framing Alignment Bits Source Select
Specifies source of the Framing Alignment bits, which include FAS
alignment bits, multiframe alignment bits, E and A bits.
0 = Internally generated and inserted into the outbound E1 frames.
1 = TxSer_n Input: Transmit Serial Input port will be source of the
FAS bits, CRC Multiframe Alignments and the E and A bits.
TABLE 19: SYNCHRONIZATION MUX REGISTER - T1 MODE
R
EGISTER 9 - T1 MODE
IT UNCTION
S
YNCHRONIZATION MUX REGISTER (SMR)
HEX ADDRESS: 0X0109
B
F
TYPE
D
EFAULT
DESCRIPTION-OPERATION
7
Reserved
-
-
Reserved
6
MFRAMEALIGN
R/W
0
Multiframe Alignment
This bit forces transmit frame counter aligns with the backplane mul-
tiframe sync.
0 = The multiframe alignment is not enforced from backplane inter-
face.
1 = The transmit multiframe is aligned with the incoming backplane
multiframe timing.
5
MSYNC
R/W
O
Tx Super Frame Sync
This bit selects the transmit input sync signal from either the frame
sync or superframe sync signals.
0 = Sync input (TxSync) is a frame sync. In 1.544MHz clock mode,
TxMSync is used, in other clock mode, TxMsync is an input
transmit
clock.
1 = Sync input is a superframe sync.
4
SYNC INV
R/W
0
Sync Inversion Select
This bit changes the direction of transmit sync and multi-sync sig-
nals.
0 = The syncs are inputs if CSS bits of CSR equal to 1, otherwise,
syncs are
outputs.
1 = The syncs are outputs if CSS bits of CSR equal to 1, otherwise,
syncs are
inputs.
45