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XRT86L30IV 参数 Datasheet PDF下载

XRT86L30IV图片预览
型号: XRT86L30IV
PDF下载: 下载PDF文件 查看货源
内容描述: 单一T1 / E1 / J1成帧器/ LIU COMBO [SINGLE T1/E1/J1 FRAMER/LIU COMBO]
分类和应用:
文件页数/大小: 284 页 / 1793 K
品牌: EXAR [ EXAR CORPORATION ]
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XRT86L30  
SINGLE T1/E1/J1 FRAMER/LIU COMBO  
REV. 1.0.1  
TABLE 24: RECEIVE  
SIGNALING & DATA  
L
INK  
S
ELECT  
REGISTER - E1 MODE  
R
EGISTER 12 - E1 MODE IGNALING & DATA  
R
ECEIVE  
S
L
INK  
S
ELECT  
R
EGISTER (RS&DLSR)  
HEX ADDRESS: 0X010C  
B
IT  
F
UNCTION  
TYPE  
D
EFAULT  
DESCRIPTION-OPERATION  
3
RxSa4ENB  
R/W  
0
This Read/Write bit is used to specify whether or not data link infor-  
mation will be transported via National Bit Sa4 (bit 3 within timeslot 0  
of non-FAS frames)  
0 = Sa4 does not carry data link information  
1 = Sa4 carries data link information  
N
OTE: This bit-field is valid only if the RxSIGDL[2:0] = “000” or “001”.  
(If the National bits have been configured to carry data link  
bits).  
2
1
0
RxSIGDL(2)  
RxSIGDL(1)  
RxSIGDL(0)  
R/W  
R/W  
R/W  
0
0
0
These three Read/Write bits are used to specify the type of data that  
is to be extracted via D/E channel, National Bits in timeslot 0 of the  
non-FAS frames, and Timeslot 16 in the outbound frames.  
D/E Channel  
0xx = Fractional Output  
1xx = Serial Signaling Output  
National Bits (Sa4-8  
)
000 = Data Link Data extracted from National bits  
001 = Data Link Data extracted from National bits  
010 = National bits forced to 1, not used to carry data link data  
011 = None (forced to 1)  
1xx = Data Link Data extracted from National bits  
Timeslot 16  
000 = Timeslot 16 is taken directly from PCM  
001 = CAS Signaling bits A,B,C,D (per time slot)  
010 = CCS Signaling bits A,B,C,D  
011 = CAS Signaling bits A,B,C,D (per time slot)  
1xx = Timeslot 16 is taken directly from PCM  
T
ABLE 25: RECEIVE  
S
IGNALING & DATA  
L
INK  
INK  
S
ELECT  
R
EGISTER (RS&DLSR) T1 MODE  
R
EGISTER 12 - T1 MODE  
RECEIVE  
SIGNALING & DATA  
L
S
ELECT  
R
EGISTER (RS&DLSR) HEX ADDRESS: 0X010C  
B
IT  
FUNCTION  
TYPE  
D
EFAULT  
DESCRIPTION-OPERATION  
7
6
5
4
Reserved  
-
-
-
Reserved  
Reserved  
Reserved  
-
RxDLBW[1]  
RxDLBW[0]  
R/W  
R/w  
0
0
Data Link Bandwidth  
00 = FDL is a 4kHz data link channel.  
01 = FDL is a 2kHz data link channel carried by old framing  
bits(1,5,9,....).  
10 = FDL is a 2kHz data link channel carried by even framing  
bits(3,7,11,....).  
3
2
RxDE[1]  
RxDE[0]  
R/W  
R/W  
0
0
DE Select  
00 = The D/E time slots are output to RxSER.  
01 = The D/E time slots are output to the LAPD controller.  
10 = The D/E time slots are output to the serial signaling output.  
11 = The D/E time slots are output to the fractional output.  
51  
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