XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
REV. 1.0.1
TABLE 15: FRAMING
SELECT
REGISTER-T1 MODE
R
EGISTER 7- T1 MODE
F
RAMING
S
ELECT EGISTER (FSR)
R
HEX ADDRESS: 0X0107
B
IT
F
UNCTION
TYPE
D
EFAULT
DESCRIPTION-OPERATION
5
J1_CRC
R/W
0
CRC Calculation in J1 Mode
Setting this bit to 1 will force CRC calculation for J1 format. The J1
CRC6 calculation is based on the actual values of all 4632 bits in a
DS1 multiframe including Fe bits instead of assuming all Fe bits to be
a one in T1 format.
4
3
ONEONLY
FASTSYNC
R/W
R/W
0
1
Allow Only One Sync Candidate
Setting this bit to 1 will enable framing search engine to declare sync
while there is one and only one candidate left.
Faster Sync Algorithm
Setting this bit to 1 will enable framing search engine to declare
SYNC condition earlier.
2
1
0
FS[2]
FS[1]
FS[0]
R/W
R/W
R/W
0
0
0
Framing Select bit 2
Framing Select bit 1
Framing Select bit 0
These three bits select the DS1 framing mode. Bit 2 is MSB and Bit
0 is LSB.
NOTE
:
Changing framing format will cause a RESYNC to be
generated automatically.
Framing
ESF
FS[2]
FS[1]
FS[0]
0
1
1
1
1
X
0
1
1
0
X
1
0
1
0
SF
N
T1DM
SLC96
TABLE 16: ALARM
G
ENERATION
REGISTER - E1 MODE
R
EGISTER 8 -E1 MODE
IT UNCTION
A
LARM
G
ENERATION EGISTER (AGR)
R
HEX ADDRESS: 0X0108
B
F
TYPE
D
EFAULT
DESCRIPTION-OPERATION
7
AUXPG
RO
0
AUXP Generation
Enables the generation of AUXP pattern which is an unframed 1010….
pattern.
0 = AUXP is disabled.
1 = AUXP is enabled.
6
LOF
R/W
0
Loss of Frame Declaration Criteria
This Read/Write bit-field is used to select the LOF or Red Alarm gener-
ation criteria the Receive E1 Framer block will employ.
0 = Receive E1 Framer declares Red Alarm unless both FAS and multi-
frame alignment are achieved.
1 = Prevents Receive E1 Framer from declaring Red Alarm condition;
FAS Alignment is maintained.
41
EXAR [ EXAR CORPORATION ]
