XRT86L30
REV. 1.0.1
SINGLE T1/E1/J1 FRAMER/LIU COMBO
TABLE 14: FRAMING
S
ELECT
R
EGISTER-E1 MODE
R
EGISTER 7- E1 MODE
IT UNCTION
F
RAMING
S
ELECT
R
EGISTER (FSR)
HEX ADDRESS: 0X0107
B
F
T
YPE
R/W
R/W
D
EFAULT
DESCRIPTION-OPERATION
5
E1 CASSEL(1)
E1 CASSEL(0)
0
0
CAS Multiframe Alignment Algorithm Select
Allows the user to select which CAS Multiframe Alignment algorithm
to employ.
4
00 = CAS Multiframe Alignment disabled
01 = CAS Multiframe Alignment Algorithm 1 enabled
10 = CAS Multiframe Alignment Algorithm 2 (G.732) enabled
11 = CAS Multiframe Alignment disabled
3
2
E1 CRCSEL(1)
E1 CRCSEL(0)
R/W
R/W
0
0
CRC Multiframe Alignment Criteria Select
Allows the user to select which CRC-Multiframe Alignment to
employ.
00 = CRC Multiframe Alignment disabled
01 = CRC Multiframe Alignment enabled. Alignment is declared if at
least one valid CRC multiframe alignment signal (0,0,1,0,1,1,E1,E2)
is observed within 8ms.
10 = CRC Multiframe Alignment enabled. Alignment is declared if at
least two valid CRC multiframe alignment signals (0,0,1,0,1,1,E1,E2)
are observed within 8ms with the time separating the two alignment
signals being multiples of 2ms.
11:CRC Multiframe Alignment enabled. Alignment is declared if at
least 3 valid CRC multiframe alignment signals (0,0,1,0,1,1,E1,E2)
are observed within 8ms with the time separating the two alignment
signals being multiples of 2ms.
1
0
E1 CKSEQ_ENB
E1 FASSEL
R/W
R/W
0
0
Check Sequence Enable-FAS Alignment
Enable/Disable frame check sequence in FAS alignment process.
0 = Disables Frame Check Sequence
1 = Enables Frame Check Sequence‘
FAS Alignment Algorithm Select
Specifies which algorithm the Receive E1 Framer block uses in its
search for FAS Alignment.
0 = Algorithm 1
1 = Algorithm 2
TABLE 15: FRAMING
SELECT
REGISTER-T1 MODE
R
EGISTER 7- T1 MODE
IT UNCTION
F
RAMING
S
ELECT EGISTER (FSR)
R
HEX ADDRESS: 0X0107
B
F
TYPE
D
EFAULT
DESCRIPTION-OPERATION
7
SIGFRAME
R/W
0
Enable Signaling Update
Setting this bit to 1 will enable signaling update (transmit and
receive) on the superframe boundary. Otherwise, signaling data will
be updated once it is received.
6
CRCDIAG
R/W
0
Force CRC Errors
Setting this bit to 1 will force CRC error on transmit stream.
40
EXAR [ EXAR CORPORATION ]
