XRT86L30
REV. 1.0.1
SINGLE T1/E1/J1 FRAMER/LIU COMBO
FIGURE 5. MOTOROLA 68K µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS
MOTOROLA ASYCHRONOUS MODE
READ OPERATION
WRITE OPERATION
ALE_TS
ADDR[11:0]
CS
t0
t0
Valid Address
Valid Address
t3
t3
Valid Data for Readback
DATA[7:0]
RD_WE
Data Available to Write Into the LIU
t1
t1
WR_R/W
t2
RDY_DTACK
t2
TABLE 8: MOTOROLA 68K MICROPROCESSOR
INTERFACE
TIMING
SPECIFICATIONS
S
YMBOL
P
ARAMETER
MIN
M
AX
UNITS
t
t
t
Valid Address to CS Falling Edge
0
-
ns
ns
ns
ns
ns
0
1
2
CS Falling Edge to DS (Pin RD_WE) Assert
DS Assert to DTACK Assert
65
-
-
90
-
NA
DS Pulse Width (t )
90
0
2
t
CS Falling Edge to AS (Pin ALE_TS) Falling Edge
-
3
3.2.1
DMA Read/Write Operations
The XRT86L30 Framer contains two DMA Controller Interfaces which provide support for all four framers within
the chip. The purpose of the two DMA Controllers is to facilitate the rapid block transfer of data between an
external memory location and the on-chip HDLC buffers via the Microprocessor Interface.
DMA-0 Write DMA Interface
DMA 0 Controller Interface handles data transfer between external memory and the selected Transmit HDLC
Buffer.
The DMA cycle starts when the XRT86L30 asserts the REQ0 output pin. The external DMA Controller then
responds by asserting the ACK0 input pin. The contents of the Microprocessor Interface bi-directional data bus
are latched into the XRT86L30 each time the WR (Write Strobe) input pin is strobed “Low”.
The XRT86L30 ends the DMA cycle by negating the DMA request input (REQ0) while WR is still active. The
external DMA Controller acknowledges the end of DMA Transfer by driving the ACK0 input pin “High”.
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EXAR [ EXAR CORPORATION ]
