XRT86L30
REV. 1.0.1
SINGLE T1/E1/J1 FRAMER/LIU COMBO
3.3
Memory Mapped I/O Addressing
TABLE 9: XRT86L30 FRAMER/LIU REGISTER
MAP
A
DDRESS [11:0]
CONTENTS
0100h - 01FFh
0300h - 03FFh
0500h - 05FFh
0600h - 06FFh
0700h - 07FFh
0900h - 09FFh
0B00h - 0BFFh
0C00h - 0DFFh
0F00h - 0FFFh
Control Register (Framer Block)
Time Slot (Payload) Control (Framer Block)
Receive Signaling Array (Framer Block)
LAPDn Buffer 0 (Framer Block)
LAPDn Buffer 1 (Framer Block)
Performance Monitor (Framer Block)
Interrupt Generation/Enable (Framer Block)
Reserved
Line Interface Control (LIU Block)
30