XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
REV. 1.0.1
FIGURE 3. INTEL µP INTERFACE
S
IGNALS
D
URING
PROGRAMMED I/O READ AND WRITE OPERATIONS
READ OPERATION
WRITE OPERATION
ALE = 1
t0
t0
ADDR[11:0]
CS
Valid Address
Valid Address
DATA[7:0]
Valid Data for Readback
Data Available to Write Into the LIU
t1
RD
t3
WR
t2
t4
RDY
TABLE 6: INTEL
M
ICROPROCESSOR
I
NTERFACE
TIMING
SPECIFICATIONS
S
YMBOL
P
ARAMETER
MIN
M
AX
UNITS
t
t
t
Valid Address to CS Falling Edge
CS Falling Edge to RD Assert
RD Assert to RDY Assert
0
-
ns
ns
ns
ns
ns
ns
ns
0
1
2
65
-
-
90
-
NA
RD Pulse Width (t )
90
65
-
2
t
t
CS Falling Edge to WR Assert
WR Assert to RDY Assert
-
3
4
90
-
NA
WR Pulse Width (t )
90
4
25
EXAR [ EXAR CORPORATION ]
