XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
REV. 1.0.1
3.4
Description of the Control Registers
TABLE 10: REGISTER
S
UMMARY
YMBOL
R
EG
#
FUNCTION
S
H
EX
MODE
Control Registers (0x0100 - 0x01FF)
0
1
2
3
4
5
6
7
Clock and Select Register
CSR
LICR
0x0100
0x0101
0x0102
0x0103
0x0104
0x0105
0x0106
0x0107
0x0107
0x0108
0x0108
0x0109
0x0109
0x010A
0x010A
0x010B
0x010B
0x010C
0x010C
0x010D
0x010E
0x010F
0x0110
0x0111
0x0112
0x0112
0x0113
0x0114
0x0115
0x0116
T1/E1
T1/E1
T1/E1
-
Line Interface Control Register
General Purpose Input/Output Control
Reserved
GPIOCR
-
Reserved
-
-
Reserved
-
-
-
Reserved
-
Framing Select Register
FSR
E1
Framing Select Register
T1
8
Alarm Generation Register
Alarm Generation Register
Synchronization MUX Register
Synchronization MUX Register
Transmit Signaling and Data Link Select Register
Transmit Signaling and Data Link Select Register
Framing Control Register
AGR
SMR
E1
T1
9
E1
T1
10
11
12
TSDLSR
FCR
E1
T1
E1
Framing Control Register
T1
Receive Signaling & Data Link Select Register
Receive Signaling & Data Link Select Register
Signaling Change Register 0
Signaling Change Register 1
Signaling Change Register 2
Signaling Change Register 3
Receive National Bits Register
Receive Extra Bits Register
Receive Interface Control
RS&DLSR
E1
T1
13
14
15
16
17
18
SCR0
SCR1
T1/E1
T1/E1
T1/E1
E1
SCR2
SCR3
RNBR
E1
REBR
E1
RICR
T1
19
20
21
22
Data Link Control Register 1
Transmit Data Link Byte Count Register 1
Receive Data Link Byte Count Register 1
Slip Buffer Control Register
DLCR1
TDLBCR1
RDLBCR1
SBCR
T1/E1
T1/E1
T1/E1
T1/E1
31
EXAR [ EXAR CORPORATION ]
