XRT86L30
REV. 1.0.1
SINGLE T1/E1/J1 FRAMER/LIU COMBO
3.1
Intel Mode Programmed I/O Access (Asynchronous)
If the XRT86L30 is interfaced to an Intel type µP, then it should be configured to operate in the Intel mode. Intel
type Read and Write operations are described below.
Intel Mode Read Cycle
Whenever an Intel-type µP wishes to read the contents of a register, it should do the following.
1. Place the address of the target register on the address bus input pins ADDR[11:0].
2. While the µP is placing this address value on the address bus, the address decoding circuitry should
assert the CS pin of the XRT86L30, by toggling it "Low". This action enables further communication
between the µP and the XRT86L30 microprocessor interface block.
3. Toggle the ALE input pin "High". This step enables the address bus input drivers, within the microproces-
sor interface block of the XRT86L30.
4. The µP should then toggle the ALE pin "Low". This step causes the XRT86L30 to latch the contents of the
address bus into its internal circuitry. At this point, the address of the register has now been selected.
5. Next, the µP should indicate that this current bus cycle is a Read operation by toggling the RD input pin
"Low". This action also enables the bi-directional data bus output drivers of the XRT86L30.
6. After the µP toggles the Read signal "Low", the XRT86L30 will toggle the RDY output pin "Low". The
XRT86L30 does this in order to inform the µP that the data is available to be read by the µP, and that it is
ready for the next command.
7. After the µP detects the RDY signal and has read the data, it can terminate the Read Cycle by toggling the
RD input pin "High".
NOTE: ALE can be tied “High” if this signal is not available.
The Intel Mode Write Cycle
Whenever an Intel type µP wishes to write a byte or word of data into a register within the XRT86L30, it should
do the following.
1. Place the address of the target register on the address bus input pins ADDR[11:0].
2. While the µP is placing this address value on the address bus, the address decoding circuitry should
assert the CS pin of the XRT86L30, by toggling it "Low". This action enables further communication
between the µP and the XRT86L30 microprocessor interface block.
3. Toggle the ALE input pin "High". This step enables the address bus input drivers, within the microproces-
sor interface block of the XRT86L30.
4. The µP should then toggle the ALE pin "Low". This step causes the XRT86L30 to latch the contents of the
address bus into its internal circuitry. At this point, the address of the register has now been selected.
5. The µP should then place the byte or word that it intends to write into the target register, on the bi-direc-
tional data bus DATA[7:0].
6. Next, the µP should indicate that this current bus cycle is a Write operation by toggling the WR input pin
"Low". This action also enables the bi-directional data bus input drivers of the XRT86L30.
7. After the µP toggles the Write signal "Low", the XRT86L30 will toggle the RDY output pin "Low". The
XRT86L30 does this in order to inform the µP that the data has been written into the internal register loca-
tion, and that it is ready for the next command.
NOTE: ALE can be tied “High” if this signal is not available.
The Intel Read and Write timing diagram is shown in Figure 3. The timing specifications are shown in Table 6.
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