XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
REV. 1.0.1
FIGURE 4. MOTOROLA µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS
READ OPERATION
WRITE OPERATION
TS
tdc
uPCLK
tcp
t0
t0
Valid Address
Valid Address
ADDR[11:0]
CS
t3
t3
Valid Data for Readback
DATA[7:0]
WE
Data Available to Write Into the LIU
t1
t1
R/W
TA
t2
t2
TABLE 7: INTEL
M
ICROPROCESSOR
I
NTERFACE
TIMING
SPECIFICATIONS
S
YMBOL
P
ARAMETER
MIN
M
AX
UNITS
t
t
t
Valid Address to CS Falling Edge
CS Falling Edge to WE Assert
WE Assert to TA Assert
0
-
ns
ns
ns
ns
0
1
2
0
-
-
90
-
NA
WE Pulse Width (t )
90
0
2
t
CS Falling Edge to TS Falling Edge
-
3
t
µ
PCLK Duty Cycle
40
20
60
-
%
dc
cp
t
µPCLK Clock Period
ns
27
EXAR [ EXAR CORPORATION ]
