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XRT86L30IV 参数 Datasheet PDF下载

XRT86L30IV图片预览
型号: XRT86L30IV
PDF下载: 下载PDF文件 查看货源
内容描述: 单一T1 / E1 / J1成帧器/ LIU COMBO [SINGLE T1/E1/J1 FRAMER/LIU COMBO]
分类和应用:
文件页数/大小: 284 页 / 1793 K
品牌: EXAR [ EXAR CORPORATION ]
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XRT86L30  
REV. 1.0.1  
SINGLE T1/E1/J1 FRAMER/LIU COMBO  
6.9  
D/E Time Slot Transmit HDLC Controller Block V5.1 or V5.2 Interface  
V5.2 protocol specifies a provision for transmitting simultaneous LAPD messages. Since only one message  
can be sent through the datalink bits at one time, an alternative path for communication is offered within the  
framer block. This alternative path is known as D or E channel which can be transmitted through one or more  
of the DS-0 time slots. D channel is used primarily for data link applications. E channel is used primarily for  
signaling for circuit switching with multiple access configurations. A range of time slots can be dedicated to  
HDLC1, while a different range of time slots can be dedicated to HDLC2 to support V5.2. In addition, HDLC3  
can be used to transmit a third LAPD message if desired. The HDLC controllers are implemented in the same  
manner as the datalink described above with the exception of the data link source select bits.  
6.10 Automatic Performance Report (APR)  
The APR feature allows the system to transmit PMON status within a LAPD Framing format A at one second  
intervals or within a single shot report. The data octets 5 through 12 within the LAPD frame are replaced with  
the PMON status for the previous one second interval.  
TABLE 169: FRAMING FORMAT FOR PMON STATUS INSERTED WITHIN LAPD BY INITIATING APR  
Octet Number  
8
7
6
5
4
3
2
1
Time (s)  
1
2
3
4
Flag = 01111110  
SAPI = 001110  
TEI = 0000000  
CR  
EA=0  
EA=1  
Control = 00000011 = Unacknowledged Frame  
5
6
G3  
FE  
G3  
FE  
G3  
FE  
G3  
FE  
LV  
SE  
LV  
SE  
LV  
SE  
LV  
SE  
G4  
LB  
G4  
LB  
G4  
LB  
G4  
LB  
U1  
G1  
U1  
G1  
U1  
G1  
U1  
G1  
U2  
R
G5  
G2  
G5  
G2  
G5  
G2  
G5  
G2  
SL  
Nm  
SL  
G6  
Ni  
T0  
7
U2  
R
G6  
Ni  
T0 - 1  
T0 - 2  
T0 - 3  
8
Nm  
SL  
9
U2  
R
G6  
Ni  
10  
11  
Nm  
SL  
U2  
R
G6  
Ni  
12  
13  
14  
15  
Nm  
FCS  
FCS  
Flag = 01111110  
NOTE: The right most bit (bit 1) is transmitted first for all fields except for the two bytes of the FCS that are transmitted left  
most bit (bit 8) first.  
6.10.1 Bit Value Interpretation  
G1 = 1 if number of CRC error events is equal to 1  
G2 = 1 if number of CRC error events is greater than 1 or equal to 5  
G3 = 1 if number of CRC error events is greater than 5 or equal to 10  
G4 = 1 if number of CRC error events is greater than 10 or equal to 100  
G5 = 1 if number of CRC error events is greater than 100 or equal to 319  
G6 = 1 if number of CRC error events is equal to 320  
SE = 1 if a severely errored framing event occurs (FE shall be 0)  
FE = 1 if a framing synchronization bit error event occurs (SE shall be 0)  
LV = 1 if a line code violation event occurs  
SL = 1 if slip event within the slip buffer occurs  
LB = 1 if payload loopback is activated  
U1 = Not Used (default = 0)  
168  
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