XRT86L30
REV. 1.0.1
SINGLE T1/E1/J1 FRAMER/LIU COMBO
address, control and information fields; the ones complement of the resulting remainder is transmitted as the
16-bit FCS.
As a typical implementation at the receiver, the initial content of the register of the device computing the
remainder is preset to all 1s. The final remainder, after multiplication by x16 and then division (modulo 2) by the
generator polynomial x16 + x12 + x5 + 1 of the serial incoming protected bits and the FCS, will be
0001110100001111 (x15 through x0, respectively) in the absence of transmission errors.
6.7.14 Transparency (Zero Stuffing)
A transmitting data link layer entity shall examine the frame content between the opening and closing flag
sequences, (address, control, information and FCS field) and shall insert a 0 bit after all sequences of five
contiguous 1 bits (including the last five bits of the FCS) to ensure that an IDLE flag or an Abort sequence is
not simulated within the frame. A receiving data link layer entity shall examine the frame contents between the
opening and closing flag sequences and shall discard any 0 bit which directly follows five contiguous 1 bits.
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EXAR [ EXAR CORPORATION ]
