XRT86L30
REV. 1.0.1
SINGLE T1/E1/J1 FRAMER/LIU COMBO
TABLE 166: BLOCK
INTERRUPT
STATUS
REGISTER
R
B
EGISTER 321
IT
B
LOCK
I
NTERRUPT TATUS
S
R
EGISTER (BISR)
HEX ADDRESS: 0X0B00
FUNCTION
TYPE
D
EFAULT
DESCRIPTION-OPERATION
4
ONESEC
RUR
0
One Second Interrupt Status
Indicates if the XRT86L30 has experienced a One Second interrupt
since the last read of this register.
0 = No outstanding One Second interrupts awaiting service
1 = Outstanding One Second interrupt awaits service
3
HDLC
RO
0
HDLC Block Interrupt Status
Indicates if the HDLC block has an interrupt request awaiting ser-
vice.
0 = No outstanding interrupt requests awaiting service
1 = HDLC Block has an interrupt request awaiting service. Interrupt
Service routine should branch to and read Data LInk Status Register
(address xA,06).
NOTE: This bit-field will be reset to 0 after the microprocessor has
performed a read to the Data Link Status Register.
2
SLIP
RO
0
Slip Buffer Block Interrupt Status
Indicates if the Slip Buffer block has any outstanding interrupt
requests awaiting service.
0 = No outstanding interrupts awaiting service
1 = Slip Buffer block has an interrupt awaiting service. Interrupt Ser-
vice routine should branch to and read Slip Buffer Interrupt Status
register (address 0xXA,0x09.
N
OTE: This bit-field will be reset to 0 after the microprocessor has
performed a read of the Slip Buffer Interrupt Status
Register.
1
ALARM
RO
0
Alarm & Error Block Interrupt Status
Indicates if the Alarm & Error Block has any outstanding interrupts
that are awaiting service.
0 = No outstanding interrupts awaiting service
1 = Alarm & Error Block has an interrupt awaiting service. Interrupt
SerStatus Register (address xA,02)
N
OTE: This bit-field will be reset to 0 after the microprocessor has
performed a read of the Alarm & Error Interrupt Status
register.
0
T1/E1 FRAME
RO
0
T1/E1 Framer Block Interrupt Status
Indicates if an T1/E1 Frame Status interrupt request is awaiting ser-
vice.
0 = No T1/E1 Frame Status interrupt is pending
1 = T1/E1 Framer Status interrupt is awaiting service.
For a given Framer, the Block Interrupt Status Register presents the "Interrupt Request" status of each
"Interrupt Block" within the Framer. The purpose of the "Block Interrupt Status Register" is to help the mP/mC
identify which "Interrupt Block(s) have requested the interrupt. Whichever bit(s) are asserted, in this register,
identifies which block(s) have experienced an "interrupt generating" condition, as presented in Table 166.
Once the mP/mC has read this register, it can determine which "branch" within the interrupt service routine that
it must follow; in order to properly service this interrupt.
140
EXAR [ EXAR CORPORATION ]
