XRT86L30
REV. 1.0.1
SINGLE T1/E1/J1 FRAMER/LIU COMBO
TABLE 168: INTERRUPT
C
ONTROL
REGISTER
R
EGISTER 26
OD
I
NTERRUPT
C
ONTROL
R
EGISTER (ICR)
HEX ADDRESS: 0X011A
M
B
IT
FUNCTION
TYPE
D
EFAULT
DESCRIPTION-OPERATION
E
7-3
2
Reserved
-
-
Reserved
Interrupt Write-to-Clear or Reset-upon-Read Select
INT_WC_RUR
R/W
0
Configures Interrupt Status bits to either RUR or Write-to-Clear
0=Interrupt Status bit RUR
1=Interrupt Status bit Write-to-Clear
1
0
ENBCLR
R/W
R/W
0
0
Interrupt Enable Auto Clear
0=Interrupt Enable bits are not cleared after status reading
1=Interrupt Enable bits are cleared after status reading
INTRUP_ENB
Interrupt Enable for Framer_n
Enables Framer n for Interrupt Generation.
0 = Disables corresponding framer block for Interrupt Generation
1 = Enables corresponding framer block for Interrupt Generation
Setting this bit-field to "0" disables all interrupts within the Framer. Setting this bit-field to "1" enables the
Framer for interrupt generation (at the Framer Level).
NOTE: It is important to note that setting this bit-field to "1" does not enable all of the interrupts within the Framer. A given
interrupt must also be enabled at the block and source-level, before it is enabled for interrupt generation.
3.6.1.2
Configuring the "Interrupt Status Bits", within a given Framer to be "Reset-upon-Read" or
"Write-to-Clear".
The XRT86L30 Source-Level Interrupt Status Register bits can be configured to be either "Reset-upon-Read"
or "Write-to-Clear". If the user configures the Interrupt Status Registers to be "Reset-upon-Read", then when
the mP/mC is reading the interrupt status register, the following will happen.
1. The contents of the Source-Level Interrupt Status Register will automatically be reset to "0x00", following
the read operation.
2. The Interrupt Request Output pin (INT) will automatically toggle false (or "high") upon reading the Interrupt
Status Register containing the last activated interrupt status bit.
If the user configures the Interrupt Status Registers to be "Write-to-Clear", then when the mP/mC is reading the
interrupt status register, the following will happen.
1. The contents of the Source-Level Interrupt Status Register will not be cleared to "0x00", following the read
operation. The mP/mC will have to write 0x00 to the interrupt status register in order to reset the contents
of the register to 0x00.
2. Reading the Interrupt Status Register, which contains the activated bit(s) will not cause the "Interrupt
Request Output" pin (INT) to toggle false. The Interrupt Request Output pin will not toggle false until the
mP/mC has written 0x00 into this register. (Hence, the Interrupt Service Routine must include this write
operation).
The Interrupt Status Register (associated with a given framer) can be configured to be either "Reset-upon-
Read" or "Write-to-Clear" by writing the appropriate value into Bit 2, within the Interrupt Control Register as
indicated in Table 168.
Writing a "0" into this bit-field configures the Interrupt Status registers to be "Reset-upon-Read" (RUR).
Conversely, writing a "1" into this bit-field configures the Interrupt Status registers to be "Write-to-Clear".
3.6.1.3
Automatic Reset of Interrupt Enable Bits
Occasionally, the user's system (which includes the Framer IC), may experience a fault condition, such that a
"Framer Interrupt Condition" will continuously exist. If this particular interrupt has been enabled (within the
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