XRT86L30
REV. 1.0.1
SINGLE T1/E1/J1 FRAMER/LIU COMBO
3.6
The Interrupt Structure within the Framer
The XRT86L30 Framer is equipped with a sophisticated Interrupt Servicing Structure. This Interrupt Structure
includes an Interrupt Request output pin INT, numerous Interrupt Enable Registers and numerous Interrupt
Status Registers.
The Interrupt Servicing Structure, within the XRT86L30 Framer contains three levels of hierarchy:
•
•
•
The Framer Level
The Block Level
The Source Level.
The Framer Interrupt Structure has been carefully designed to allow the user to quickly determine the exact
source of this interrupt (with minimal latency) which will aid the mC/mP in determining the which interrupt
service routine to call up in order to eliminate or properly respond to the condition(s) causing the interrupt.
The XRT86L30 Framer comes equipped with registers to support the servicing of this wide array of potential
"interrupt request" sources. Table 164 lists the possible conditions that can generate interrupts.
TABLE 164: LIST OF THE
P
OSSIBLE
C
ONDITIONS THAT CAN
G
ENERATE
INTERRUPTS, IN EACH FRAMER
I
NTERRUPT
B
LOCK
I
NTERRUPTING C
ONDITION
Framer Level
Loss of RxLineClk Signal· One Second Interrupt
HDLC Controller Block
Transmit HDLC - Start of Transmission
Receive HDLC - Start of Reception
Transmit HDLC - End of Transmission
Receive HDLC - End of Reception
FCS Error
Receipt of Abort Sequence
Receipt of Idle Sequence
Slip Buffer Block
Slip Buffer Full
Slip Buffer Empty
Slip Buffer - Slip
Alarm & Error Block
Receipt of CAS Multi-frame Yellow Alarm
Detection of Loss of Signal Condition
Detection of Line Code Violation
Change in Receive Loss of Framer Condition
Change in Receive AIS Condition
Receipt of FAS Frame Yellow Alarm
T1/E1 Frame Block
Change in CAS Multi-Frame Alignment
Change in National Bits· Change in CAS Signaling Bits
Change in FAS Frame Alignment· Change in the "In Frame" Condition
Detection of "Frame Mimicking Data"
Detection of Sync (CRC-4/CRC-6) Errors
Detection of Framing Bit Errors
General Flow of Interrupt Servicing
When any of the conditions presented in Table 164 occur, (if their Interrupt is enabled), then the Framer
generates an interrupt request to the mP/mC by asserting the active-low interrupt request output pin, INT.
Shortly after the local mC/mP has detected the activated INT signal, it will enter into the appropriate user-
supplied interrupt service routine. The first task for the mP/mC, while running this interrupt service routine, may
be to isolate the source of the interrupt request down to the device level (e.g, the Framer IC), if multiple
peripheral ICs exist in the user's system. However, once the interrupting peripheral device has been identified,
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