XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
REV. 1.0.1
Framer), then the Framer will generate an interrupt request to the mP/mC. Afterwards, the mP/mC will attempt
to service this interrupt by reading the appropriate Block-level and Source-Level Interrupt Status Register.
Additionally, the local mP/mC will attempt to perform some "system-related" tasks in order to try to resolve
these conditions causing the interrupt. After the local mC/mP has attempted all of these things, the Framer IC
will negate the INT output pin. However, because this system fault still remains, the condition causing the
Framer to issue this interrupt also exists. Consequently, the Framer IC will generate another interrupt request,
which forces the mP/mC to once again attempt to service this interrupt. This phenomenon quickly results in the
local mP/mC being "tied up" in a continuous cycle of executing this one interrupt service routine. Consequently,
the mP/mC (along with portions of the overall system) now becomes non-functional.
In order to prevent this phenomenon from ever occurring, the Framer IC can be configured to automatically
reset the "interrupt enable" bits, following their activation. This feature can be implemented by writing the
appropriate value to bit 1 of the "Interrupt Control Register" as indicated in Table 168.
Writing a "1" to this bit-field configures the Framer to reset a given interrupt following activation. Writing a "0" to
this bit-field configures the Framer to leave the interrupt enabled, following its activation.
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