XR16C2850
REGISTER FUNCTIONAL DESCRIPTIONS
The following table delineates the assigned bit functions for the fifteen 2850 internal registers. The assigned
bit functions are more fully defined in the following paragraphs.
XR16C2850 ACCESSIBLE REGISTERS
A2 A1 A0
Register
[Default]
Note *5
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
General Register Set
0
0
0
0
0
0
0
0
1
RHR[XX]
THR [XX]
IER [00]
bit-7
bit-7
bit-6
bit-6
bit-5
bit-5
bit-4
bit-4
bit-3
bit-3
bit-2
bit-2
bit-1
bit-1
bit-0
bit-0
0/
-CTS
interrupt
0/
-RTS
interrupt
0/
Xoff
interrupt
0/
Sleep
mode
modem
status
interrupt
receive
line
status
interrupt
transmit
holding
register
receive
holding
register
0
0
0
1
1
1
1
1
0
0
0
0
1
0
1
FCR [00]
ISR [01]
LCR [00]
MCR [00]
LSR [60]
RCVR
trigger
(MSB)
RCVR
trigger
(LSB)
0/TX
trigger
(MSB)
0/TX
trigger
(LSB)
DMA
mode
select
XMIT
FIFO
reset
RCVR
FIFO
reset
FIFO
enable
0/
0/
0/
-RTS,
-CTS
0/
Xoff
int
priority
bit-2
int
priority
bit-1
int
priority
bit-0
int
status
FIFOs
enabled
FIFOs
enabled
divisor
latch
enable
set
break
set
parity
even
parity
parity
enable
stop
bits
word
length
bit-1
word
length
bit-0
Clock
select
0/
IRRT
enable
0/
Xon
Any
loop
back
INT
Enable
-OP1
-RTS
-DTR
0/
FIFO
error
THR &
TSR
empty
THR
empty
break
interrupt
framing
error
parity
error
overrun
error
receive
data
ready
1
1
1
1
0
1
MSR [00]
-CD
bit-7
-RI
-DSR
bit-5
-CTS
bit-4
delta
-CD
delta
-RI
delta
-DSR
delta
-CTS
SCPAD [FF]
bit-6
bit-3
bit-2
bit-1
bit-0
Special Register Set: Note *3
0
0
0
0
0
1
DLL [00]
DLM [00]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-9
bit-0
bit-8
bit-15
bit-14
bit-13
bit-12
bit-11
bit-10
Rev. 1.00P
16
EXAR [ EXAR CORPORATION ]
