EM638165
EtronTech
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
Burst
Stop
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
The burst ends after a delay equal to the CAS# Latency
CAS# Latency=2
tCK2, DQ
DOUT A0
DOUT A1
DOUT A0
DOUT A2
DOUT A1
DOUT A3
DOUT A2
CAS# Latency=3
DOUT A3
t
CK3, DQ
Figure 17. Termination of a Burst Read Operation
＞
4, CAS# Latency = 2, 3)
(Burst Length
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Burst
Stop
NOP
WRITE A
DIN A0
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
don’t care
DIN A1
DIN A2
DQ
Figure 18. Termination of a Burst Write Operation
(Burst Length = X)
11 Device Deselect command (CS# = "H")
The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE# and
Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar to the No
Operation command.
12 AutoRefresh command
(RAS# = "L", CAS# = "L", WE# = "H", CKE = "H", A0-A11 = Don't care)
The AutoRefresh command is used during normal operation of the SDRAM and is analogous to CAS#-
before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it must be
issued each time a refresh is required. The addressing is generated by the internal refresh controller.
This makes the address bits a "don't care" during an AutoRefresh command. The internal refresh counter
increments automatically on every auto refresh cycle to all of the rows. The refresh operation must be
performed 4096 times within 64ms. The time required to complete the auto refresh operation is specified
by tRC(min.). To provide the AutoRefresh command, all banks need to be in the idle state and the device
must not be in power down mode (CKE is high in the previous cycle). This command must be followed by
NOPs until the auto refresh operation is completed. The precharge time requirement, tRP(min), must be
met before successive auto refresh operations are performed.
13 SelfRefresh Entry command
(RAS# = "L", CAS# = "L", WE# = "H", CKE = "L", A0-A11 = Don't care)
The SelfRefresh is another refresh mode available in the SDRAM. It is the preferred refresh mode for
data retention and low power operation. Once the SelfRefresh command is registered, all the inputs to
the SDRAM become "don't care" with the exception of CKE, which must remain LOW. The refresh
addressing and timing is internally generated to reduce power consumption. The SDRAM may remain in
SelfRefresh mode for an indefinite period. The SelfRefresh mode is exited by restarting the external clock
and then asserting HIGH on CKE (SelfRefresh Exit command).
14 SelfRefresh Exit command
This command is used to exit from the SelfRefresh mode. Once this command is registered, NOP or
Device Deselect commands must be issued for tXSR(min.) because time is required for the completion of
any bank currently being internally refreshed. If auto refresh cycles in bursts are performed during normal
operation, a burst of 4096 auto refresh cycles should be completed just prior to entering and just after
exiting the SelfRefresh mode.
Rev. 5.2
15
Rev. 5.2
Dec. /2013
ETRON [ ETRON TECHNOLOGY, INC. ]
