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EM638165TS-7IG 参数 Datasheet PDF下载

EM638165TS-7IG图片预览
型号: EM638165TS-7IG
PDF下载: 下载PDF文件 查看货源
内容描述: [4M x 16 bit Synchronous DRAM (SDRAM)]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 53 页 / 517 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
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EM638165  
EtronTech  
Table 16. Electrical Characteristics and Recommended A.C. Operating Conditions  
±
(VDD = 3.3V 0.3V, TA = - 40~85°C) (Note: 5, 6, 7, 8)  
-5I  
-6I  
-7I  
Symbol  
A.C. Parameter  
Row cycle time  
Unit Note  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
tRC  
55  
-
60  
-
63  
-
(same bank)  
RAS# to CAS# delay  
(same bank)  
tRCD  
tRP  
tRRD  
tRAS  
15  
15  
10  
40  
-
18  
18  
12  
42  
-
21  
21  
14  
42  
-
Precharge to refresh/row activate  
command (same bank)  
-
-
-
-
-
-
ns  
Row activate to row activate delay  
(different banks)  
Row activate to precharge time  
(same bank)  
100K  
100K  
100K  
Write recovery time  
tWR  
2
1
-
2
1
-
2
1
-
tCK  
CAS# to CAS# Delay time  
-
tCCD  
-
-
9
CL* = 2  
10  
7
-
-
-
9
-
tCK  
Clock cycle time  
CL* = 3  
-
5
-
6
-
10  
10  
10  
Clock high time  
Clock low time  
2.5  
2.5  
-
-
tCH  
tCL  
2
-
2.5  
2.5  
-
-
-
2
-
-
CL* = 2  
CL* = 3  
6
-
-
6
Access time from CLK  
(positive edge)  
tAC  
-
5.4  
-
4.5  
-
5.4  
ns  
9
Data output hold time  
2.5  
0
-
tOH  
tLZ  
2
-
2.5  
0
-
Data output low impedance  
Data output high impedance  
-
0
-
-
-
5.4  
8
tHZ  
-
4.5  
-
5.4  
Data/Address/Control Input set-up time  
Data/Address/Control Input hold time  
Power Down Exit set-up time  
1.5  
0.8  
IS+tCK  
2
-
10  
10  
tIS  
1.5  
0.8  
-
1.5  
0.8  
-
-
tIH  
-
-
t
-
tPDE  
tMRD  
tREFI  
tXSR  
tIS+tCK  
-
tIS+tCK  
-
Mode Register Set Command Cycle Time  
Average Refresh Interval Time  
-
15.6  
-
tCK  
µs  
ns  
2
-
-
15.6  
-
2
-
-
15.6  
-
-
Exit Self-Refresh to any Command  
t
RC+tIS  
tRC+tIS  
tRC+tIS  
*
CL is CAS Latency  
Note:  
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the  
device.  
2. All voltages are referenced to VSS. VIH (Max) = 4.6V for pulse width 3ns. VIL(Min) = -1.0V for pulse width  
3ns.  
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the  
minimum value of tCK and tRC. Input signals are changed one time during every 2 tCK.  
4. These parameters depend on the output loading. Specified values are obtained with the output open.  
5. Power-up sequence is described in Note 11.  
6. A.C. Test Conditions  
Rev. 5.2  
19  
Rev. 5.2  
Dec. /2013  
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