EtronTech
EM636165-XXI
14 Clock Suspend Mode Entry / PowerDown Mode Entry command (refer to Figures 6, 7, and 8 in
Timing Waveforms)
1M x 16 SDRAM
(CKE = "L")
When the SDRAM is operating the burst cycle, the internal CLK is suspended(masked) from
the subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held
intact while CLK is suspended. On the other hand, when both banks are in the idle state, this
command performs entry into the PowerDown mode. All input and output buffers (except the CKE
buffer) are turned off in the PowerDown mode. The device may not remain in the Clock Suspend or
PowerDown state longer than the refresh period (64ms) since the command does not perform any
refresh operations.
15 Clock Suspend Mode Exit / PowerDown Mode Exit command (refer to Figures 6, 7, and 8 in Timing
Waveforms, CKE= "H")
When the internal CLK has been suspended, the operation of the internal CLK is reinitiated
from the subsequent cycle by providing this command (asserting CKE "HIGH"). When the device is
in the PowerDown mode, the device exits this mode and all disabled buffers are turned on to the
active state. tPDE(min.) is required when the device exits from the PowerDown mode. Any
subsequent commands can be issued after one clock cycle from the end of this command.
16 Data Write / Output Enable, Data Mask / Output Disable command (LDQM/UDQM = "L", "H")
During a write cycle, the LDQM/UDQM signal functions as a Data Mask and can control every
word of the input data. During a read cycle, the LDQM/UDQM functions as the controller of output
buffers. LDQM/UDQM is also used for device selection, byte selection and bus control in a memory
system. LDQM controls DQ0 to DQ7, UDQM controls DQ8 to DQ15.
Preliminary
16
Rev. 1.1 Apr. 2005
ETRON [ ETRON TECHNOLOGY, INC. ]
