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EM636165-XXI 参数 Datasheet PDF下载

EM636165-XXI图片预览
型号: EM636165-XXI
PDF下载: 下载PDF文件 查看货源
内容描述: 1Mega ×16同步DRAM (SDRAM)的 [1Mega x 16 Synchronous DRAM (SDRAM)]
分类和应用: 动态存储器
文件页数/大小: 73 页 / 756 K
品牌: ETRON [ ETRON TECHNOLOGY, INC. ]
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EtronTech  
EM636165-XXI  
1M x 16 SDRAM  
6. A.C. Test Conditions  
LVTTL Interface  
Reference Level of Output Signals  
Output Load  
1.4V / 1.4V  
Reference to the Under Output Load (B)  
Input Signal Levels  
2.4V / 0.4V  
1ns  
Transition Time (Rise and Fall) of Input Signals  
Reference Level of Input Signals  
1.4V  
1.4V  
3.3V  
50W  
1.2kW  
50W  
Z0=  
Output  
Output  
30pF  
30pF  
870W  
LVTTL D.C. Test Load (A)  
LVTTL A.C. Test Load (B)  
7. Transition times are measured between VIH and VIL. Transition(rise and fall) of input signals are in a fixed  
slope (1 ns).  
8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference  
levels.  
9. These parameters account for the number of clock cycle and depend on the operating frequency of the  
clock as follows:  
the number of clock cycles = specified value of timing/Clock cycle time  
(count fractions as a whole number)  
10.If clock rising time is longer than 1 ns, ( tR / 2 -0.5) ns should be added to the parameter.  
11.Assumed input rise and fall time tT ( tR & tF ) = 1 ns  
If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns  
should be added to the parameter.  
12. Power up Sequence  
Power up must be performed in the following sequence.  
1) Power must be applied to VDD and VDDQ(simultaneously) when all input signals are held "NOP" state  
and both CKE = "H" and LDQM/UDQM = "H." The CLK signals must be started at the same time.  
2) After power-up, a pause of 200mseconds minimum is required. Then, it is recommended that  
LDQM/UDQM is held "HIGH" (VDD levels) to ensure DQ output is in high impedance.  
3) Both banks must be precharged.  
4) Mode Register Set command must be asserted to initialize the Mode register.  
5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of  
the device.  
Preliminary  
20  
Rev. 1.1 Apr. 2005  
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