Document No.: FT_000288
FT232H SINGLE CHANNEL HI-SPEED USB TO MULTIPURPOSE UART/FIFO IC
Datasheet Version 1.8
Clearance No.: FTDI #199
When SS_n is inactive the write buffer and read buffer status is reflected on the MIOSIO[0] and MISO
signals respectively. When the master wishes to initiate a data transfer, SS_n becomes active. As soon as
SS_n becomes active the SPI slave immediately stops driving the MIOSIO[0] signal and SPI master is not
allowed to begin driving the MIOSIO[0] signal until the first clock edge, this ensures that bus contention
is avoided.
On the first clock edge the command is shifted out for 7 clocks, on the 8th clock cycle a bus turnaround is
required. The bus turnaround is required as the slave may be required to drive the MIOSIO[0] bus with
read data. The data phase occurs in response to the command and so long as SS_n remains active. The
data phase in 1-bit mode requires 8 clock cycles where the MIOSIO[0] signal transfers the requested
write or read data. The MISO signal indicates to the master the success of the transfer with an ACK or
NAK.
The status is reflected through the whole of the data phase and is valid from the first clock edge. If the
master is writing data to the slave, then on the last clock edge before it de-asserts SS_n must tri-state
the MIOSIO[0] signal to enable the bus to be “turned” around as when SS_n becomes inactive the
FT1248 slave shall begin to drive the write buffer status onto the MIOSIO[0] signal. When the SPI slave
is driving the MIOSIO[0] (the master is reading data) no bus turnaround is required as when SS_n
becomes inactive it is required to drive the write buffer status to the FT1248 master.
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