Document No.: FT_000288
FT232H SINGLE CHANNEL HI-SPEED USB TO MULTIPURPOSE UART/FIFO IC
Datasheet Version 1.8
Clearance No.: FTDI #199
4.6 FT1248 Interface Mode Description
The FT232H supports a half duplex FT1248 Interface that provides a flexible data communication and
high performance interface between the FT232H as a FT1248 slave and an external FT1248 master. The
FT1248 protocol is a dynamic bi-directional data bus interface that can be configured as 1, 2, 4, or 8-bits
wide.
FPGA (FT1248 Master)
FT232H (FT1248 Slave)
SCLK
SCLK
MIOSIO
[7:0]
MIOSIO
MISO
SS#
MISO
SS#
Figure 4.7 FT1248 Bus with Single Master and Slave.
In the FT1248 there are 3 distinct phases:
While SS_n is inactive, the FT1248 reflects the status of the write buffer and read buffers on the
MIOSIO[0] and MISO wires respectively. Additionally, the FT1248 slave block supports multiple slave
devices where a master can communicate with multiple FT1248 slave devices. When the slave is sharing
buses with other FT1248 slave devices, the write and read buffer status cannot be reflected on the
MIOSIO[0] and MISO wires during SS_n inactivity as this would cause bus contention. Therefore, it is
possible for the user to select whether they wish to have the buffer status switched on or off during
inactivity. When SS_n is active a command/bus size phase occurs first. Following the command phase is
the data phase, for each data byte transferred the FT1248 slave drives an ACK/NAK status onto the MISO
wire. The master can send multiple data bytes so long as SS_n is active, if a unsuccessful data transfer
occurs, i.e. a NAK happens on the MISO wire then the master should immediately abort the transfer by
de-asserting SS_n.
CLK
SCLK
WRITE
READ
SS_n
WRITE DATA
BUS TURNAROUND
CMD
WDATA
0
WDATA 1
TXE#
CMD
RDATA0
RDATA1
RDATA2
TXE#
MIOSIO[0]
TXE#
RXF#
STATUS
STATUS
STATUS
MISO
RXF#
RXF#
STATUS
STATUS
Figure 4.8: FT1248 Basic Waveform Protocol.
Section 4.6.2 illustrates the FT1248 write and read protocol operating in 1-bit mode. For details regarding
2-bit, 4-bit and 8-bit modes, please refer to application note AN_167_FT1248 Parallel Serial Interface
Basics available at http://www.ftdichip.com.
Copyright © 2012 Future Technology Devices International Limited
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