M32L1632512A
Read & Write Cycle at Different Bank @ Burst Length =4
11
12
13
15
17
19
1
2
3
9
10
14
16
18
0
6
8
4
5
7
C L O C K
C K E
H IG H
C S
R A S
C A S
R A a
C A a
C B b R A c
R B b
C A c
A D D R
A10
A9
R A a
R B b
R A c
tCD L
* N ot e 1
W E
D S F
D Q M
D Q C L = 2
QAc 1 QAc 2
QAc 0 QAc 1
D Bb0 D Bb1
D Bb0 D Bb1
D Bb3
D Bb3
QAa0 QAa1 QAa2 QAa3
D Bb2
D Bb2
QA c 0
QAa0 QAa1 QAa2 QAa3
C L = 3
P re c ha r ge
( A- B an k )
R ow A c t i v e
(A - B an k )
Rea d
(A - Ba n k )
R ea d
( A - Ba n k )
W r i t e
( B - B an k )
R o w A c t i v e
( B- B an k )
R o w A c t i v e
( A - B an k )
:D o n ' t C a r e
*Note : 1. CDL should be met to complete write.
t
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6 42/54
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
