ESMT
M14D5121632A (2H)
Operation Temperature Condition (TC) -40°C~95°C
AC Timing Parameter & Specifications - Contiuned
-2.5
-3
Unit
Note
Parameter
Symbol
Min.
Max.
Min.
Max.
2500
2500
-
8000
8000
-
-
-
CL=6
CL=5
CL=4
t
CK (avg)
ps
ps
13
10
Clock period
3000
3750
8000
8000
DQ output access time from
CLK/ CLK
tAC
-400
+400
-450
+450
CLK high-level width
CLK low-level width
t
CH (avg)
CL (avg)
0.48
0.48
0.52
0.52
0.48
0.48
0.52
0.52
t
t
CK (avg)
CK (avg)
13
13
t
DQS output access time from
CLK/ CLK
tDQSCK
-350
+350
-400
+400
ps
10
Clock to first rising edge of DQS
delay
tDQSS
-0.25
50
+0.25
-0.25
100
175
0.35
200
275
0.6
+0.25
t
t
t
CK (avg)
ps
Data-in and DM setup time
(to DQS)
tDS
(base)
-
-
-
-
-
-
-
-
-
-
-
-
4
5
Data-in and DM hold time
(to DQS)
tDH
(base)
125
0.35
175
250
0.6
ps
DQ and DM input pulse width
(for each input)
tDIPW
CK (avg)
ps
Address and Control Input
setup time
t
IS (base)
4
5
Address and Control Input hold
time
t
IH (base)
tIPW
ps
Control and Address input pulse
width
CK (avg)
DQS input high pulse width
DQS input low pulse width
tDQSH
tDQSL
0.35
0.35
-
-
0.35
0.35
-
-
t
t
CK (avg)
CK (avg)
DQS falling edge to CLK rising
setup time
tDSS
tDSH
0.2
0.2
-
-
-
0.2
0.2
-
-
-
t
t
CK (avg)
CK (avg)
ps
DQS falling edge from CLK
rising hold time
Data strobe edge to output data
edge
tDQSQ
200
240
Data-out high-impedance
window from CLK/ CLK
tHZ
-
t
AC(max.)
-
tAC(max.)
tAC(max.)
ps
ps
10
10
tLZ
(DQS)
tLZ
Data-out low-impedance window
from CLK/ CLK
tAC(min.)
2 x tAC(min.)
tAC(max.)
tAC(min.)
2 x tAC(min.)
DQ low-impedance window from
CLK/ CLK
tAC(max.)
-
tAC(max.)
-
ps
ps
10
(DQ)
Min
Min
Half clock period
tHP
6,13
(tCL(abs),tCH(abs))
(tCL(abs),tCH(abs))
DQ/DQS output hold time from
DQS
tQH
t
HP-tQHS
-
-
tHP-tQHS
-
-
ps
ps
DQ hold skew factor
tQHS
300
340
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.1 14/62
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
