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F25S04PA-86DG 参数 Datasheet PDF下载

F25S04PA-86DG图片预览
型号: F25S04PA-86DG
PDF下载: 下载PDF文件 查看货源
内容描述: 2.5V只有4兆位串行闪存,带有双输出 [2.5V Only 4 Mbit Serial Flash Memory with Dual Output]
分类和应用: 闪存
文件页数/大小: 34 页 / 382 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
(Preliminary)  
F25S04PA  
Chip Erase  
The Chip Erase instruction clears all bits in the device to FFH. A  
Chip Erase instruction will be ignored if any of the memory area is  
protected. Prior to any Write operation, the Write Enable (WREN)  
Erase instruction is initiated by executing an 8-bit command, 60H  
or C7H. CE must be driven high before the instruction is  
executed. The user may poll the Busy bit in the Software Status  
Register or wait TCE for the completion of the internal self-timed  
Chip Erase cycle. See Figure 10 for the Chip Erase sequence.  
instruction must be executed. CE must remain active low for  
the duration of the Chip-Erase instruction sequence. The Chip  
CE  
0 1 2 3 4 5 6 7  
MODE3  
SCK  
SI  
MODE0  
60 or C7  
MSB  
HIGH IMPENANCE  
SO  
Figure 10: Chip Erase Sequence  
Read Status Register (RDSR)  
The Read Status Register (RDSR) instruction allows reading of  
the status register. The status register may be read at any time  
even during a Write (Program/Erase) operation.  
When a Write operation is in progress, the Busy bit may be  
checked before sending any new commands to assure that the  
new commands are properly received by the device.  
CE must be driven low before the RDSR instruction is entered  
and remain low until the status data is read. Read Status  
Register is continuous with ongoing clock cycles until it is  
terminated by a low to high transition of the CE . See Figure 11  
for the RDSR instruction sequence.  
Figure 11: Read Status Register (RDSR) Sequence  
Elite Semiconductor Memory Technology Inc.  
Publication Date: May 2009  
Revision: 0.2  
15/34  
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