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F25S04PA-86DG 参数 Datasheet PDF下载

F25S04PA-86DG图片预览
型号: F25S04PA-86DG
PDF下载: 下载PDF文件 查看货源
内容描述: 2.5V只有4兆位串行闪存,带有双输出 [2.5V Only 4 Mbit Serial Flash Memory with Dual Output]
分类和应用: 闪存
文件页数/大小: 34 页 / 382 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
(Preliminary)  
F25S04PA  
Page Program (PP)  
The Page Program instruction allows many bytes to be  
programmed in the memory. The bytes must be in the erased  
state (FFH) when initiating a Program operation. A Page  
Program instruction applied to a protected memory area will be  
ignored.  
latched data are discarded and the last 256 bytes Data are  
guaranteed to be programmed correctly within the same page. If  
less than 256 bytes Data are sent to device, they are correctly  
programmed at the requested addresses without having any  
effects on the other bytes of the same page.  
Prior to any Write operation, the Write Enable (WREN) instruction  
CE must be driven high before the instruction is executed. The  
user may poll the Busy bit in the software status register or wait  
TPP for the completion of the internal self-timed Page Program  
operation. While the Page Program cycle is in progress, the Read  
Status Register instruction may still be accessed for checking the  
status of the Busy bit. It is recommended to wait for a duration of  
TBP before reading the status register to check the BUSY bit. The  
BUSY bit is a 1 during the Page Program cycle and becomes a 0  
when the cycle is finished and the device is ready to accept other  
instructions again. After the Page Program cycle has finished, the  
Write-Enable-Latch (WEL) bit in the Status Register is cleared to  
0. See Figure 7 for the Page Program sequence.  
must be executed. CE must remain active low for the duration  
of the Page Program instruction. The Page Program instruction is  
initiated by executing an 8-bit command, 02H, followed by  
address bits [A23-A0]. Following the address, at least one byte  
Data is input (the maximum of input data can be up to 256 bytes).  
If the 8 least significant address bits [A7-A0] are not all zero, all  
transmitted data that goes beyond the end of the current page  
are programmed from the start address of the same page (from  
the address whose 8 least significant bits [A7-A0] are all zero).  
If more than 256 bytes Data are sent to the device, previously  
Figure 7: Page Program Sequence  
Elite Semiconductor Memory Technology Inc.  
Publication Date: May 2009  
Revision: 0.2  
13/34  
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