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F25S04PA-86DG 参数 Datasheet PDF下载

F25S04PA-86DG图片预览
型号: F25S04PA-86DG
PDF下载: 下载PDF文件 查看货源
内容描述: 2.5V只有4兆位串行闪存,带有双输出 [2.5V Only 4 Mbit Serial Flash Memory with Dual Output]
分类和应用: 闪存
文件页数/大小: 34 页 / 382 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
(Preliminary)  
F25S04PA  
64K Byte Block Erase  
The 64K-byte Block Erase instruction clears all bits in the  
selected block to FFH. A Block Erase instruction applied to a  
protected memory area will be ignored. Prior to any Write  
operation, the Write Enable (WREN) instruction must be  
-A0]. Address bits [AMS -A16] (AMS = Most Significant address) are  
used to determine the block address (BAX), remaining address  
bits can be VIL or VIH. CE must be driven high before the  
instruction is executed. The user may poll the Busy bit in the  
Software Status Register or wait TBE for the completion of the  
internal self-timed Block Erase cycle. See Figure 8 for the Block  
Erase sequence.  
executed. CE must remain active low for the duration of the any  
command sequence. The Block Erase instruction is initiated by  
executing an 8-bit command, D8H, followed by address bits [A23  
Figure 8: 64K-byte Block Erase Sequence  
4K Byte Sector Erase  
The Sector Erase instruction clears all bits in the selected sector  
to FFH. A Sector Erase instruction applied to a protected memory  
area will be ignored. Prior to any Write operation, the Write  
[AMS -A12] (AMS = Most Significant address) are used to determine  
the sector address (SAX), remaining address bits can be VIL or  
VIH. CE must be driven high before the instruction is executed.  
The user may poll the Busy bit in the Software Status Register or  
wait TSE for the completion of the internal self-timed Sector Erase  
cycle. See Figure 9 for the Sector Erase sequence.  
Enable (WREN) instruction must be executed. CE must remain  
active low for the duration of the any command sequence. The  
Sector Erase instruction is initiated by executing an 8-bit  
command, 20H, followed by address bits [A23 -A0]. Address bits  
CE  
15 16  
31  
23 24  
0 1 2 3 4 5 6 7 8  
MODE3  
MODE0  
SCK  
SI  
20  
ADD.  
MSB  
ADD.  
ADD.  
MSB  
HIGH IMPENANCE  
SO  
Figure 9: 4K-byte Sector Erase Sequence  
Elite Semiconductor Memory Technology Inc.  
Publication Date: May 2009  
Revision: 0.2 14/34  
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