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F25S04PA-86DG 参数 Datasheet PDF下载

F25S04PA-86DG图片预览
型号: F25S04PA-86DG
PDF下载: 下载PDF文件 查看货源
内容描述: 2.5V只有4兆位串行闪存,带有双输出 [2.5V Only 4 Mbit Serial Flash Memory with Dual Output]
分类和应用: 闪存
文件页数/大小: 34 页 / 382 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
(Preliminary)  
F25S04PA  
Write-Status-Register (WRSR)  
The Write Status Register instruction writes new values to the  
When WP is high, the lock-down function of the BPL bit is  
disabled and the BPL, TB, BP0, BP1,and BP2 bits in the status  
BP2, BP1, BP0, and BPL bits of the status register. CE must be  
driven low before the command sequence of the WRSR  
instruction is entered and driven high before the WRSR  
instruction is executed. See Figure 14 for WREN and WRSR  
instruction sequences.  
register can all be changed. As long as BPL bit is set to 0 or WP  
pin is driven high (VIH) prior to the low-to-high transition of the  
CE pin at the end of the WRSR instruction, the bits in the status  
register can all be altered by the WRSR instruction. In this case,  
a single WRSR instruction can set the BPL bit to “1” to lock down  
the status register as well as altering the TB, BP0; BP1 and BP2  
bits at the same time. See Table 4 for a summary description of  
Executing the Write Status Register instruction will be ignored  
when WP is low and BPL bit is set to “1”. When the WP is  
low, the BPL bit can only be set from “0” to “1” to lock down the  
status register, but cannot be reset from “1” to “0”.  
WP and BPL functions.  
CE  
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15  
MODE3  
MODE0  
SCK  
Stauts Register  
Data In  
06  
01  
7
6
4
3
2
0
1
SI  
5
MSB  
MSB  
HIGH IMPENANCE  
SO  
Figure 14: Write-Enable (WREN) and Write-Status-Register (WRSR)  
Elite Semiconductor Memory Technology Inc.  
Publication Date: May 2009  
Revision: 0.2 17/34  
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