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F25S04PA-86DG 参数 Datasheet PDF下载

F25S04PA-86DG图片预览
型号: F25S04PA-86DG
PDF下载: 下载PDF文件 查看货源
内容描述: 2.5V只有4兆位串行闪存,带有双输出 [2.5V Only 4 Mbit Serial Flash Memory with Dual Output]
分类和应用: 闪存
文件页数/大小: 34 页 / 382 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
(Preliminary)  
F25S04PA  
„ INSTRUCTIONS  
Instructions are used to Read, Write (Erase and Program), and  
configure the F25S04PA. The instruction bus cycles are 8 bits  
each for commands (Op Code), data, and addresses. Prior to  
executing any Page Program, Write Status Register, Sector  
Erase, Block Erase, or Chip Erase instructions, the Write Enable  
(WREN) instruction must be executed first. The complete list of  
the instructions is provided in Table 5. All instructions are  
entered and must be driven high after the last bit of the instruction  
has been shifted in (except for Read, Read ID, Read Status  
Register, Read Electronic Signature instructions). Any low to high  
transition on CE , before receiving the last bit of an instruction  
bus cycle, will terminate the instruction in progress and return the  
device to the standby mode.  
synchronized off a high to low transition of CE . Inputs will be  
accepted on the rising edge of SCK starting with the most  
Instruction commands (Op Code), addresses, and data are all  
input from the most significant bit (MSB) first.  
significant bit. CE must be driven low before an instruction is  
Table 5: Device Operation Instructions  
Bus Cycle 1~3  
4
SOUT SIN SOUT SIN SOUT SIN  
Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z  
Max.  
Freq  
Operation  
1
2
3
5
6
N
SIN  
SOUT  
SIN  
SOUT  
SIN  
X
X
SOUT  
SIN SOUT  
Read  
33 MHz 03H  
X
X
DOUT0  
X
DOUT1  
DOUT0  
X
X
cont.  
cont.  
Fast Read  
0BH Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z  
3BH A23-A16 A15-A8 A7-A0  
Fast Read Dual  
X
DOUT0~1  
cont.  
Output11,12  
Sector Erase4 (4K Byte)  
Block Erase4, (64K Byte)  
20H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z  
D8H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z  
60H /  
-
-
-
-
-
-
-
-
-
-
-
-
Chip Erase  
Hi-Z  
-
-
-
-
-
-
-
-
-
-
-
-
C7H  
Up to  
Page Program (PP)  
02H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z DIN0  
Hi-Z  
DIN1  
Hi-Z  
256 Hi-Z  
bytes  
50MHz  
~
Read Status Register  
05H Hi-Z  
01H Hi-Z  
X
DOUT  
Hi-Z  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(RDSR) 6  
Write Status Register  
(WRSR)  
DIN  
-.  
-
-
Write Enable (WREN) 9  
Write Disable (WRDI)  
Deep Power Down (DP)  
Release from Deep  
Power Down (RDP)  
Read Electronic  
06H Hi-Z  
04H Hi-Z  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
100MHz  
B9h  
Hi-Z  
ABH Hi-Z  
ABH Hi-Z  
9FH Hi-Z  
90H Hi-Z  
-
X
-
X
-
-
-
-
-
X
-
-
12H  
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
Signature (RES) 7  
Jedec Read ID  
X
8CH  
20H  
13H  
(JEDEC-ID) 8  
00H Hi-Z  
01H Hi-Z  
X
X
8CH  
12H  
X
X
12H  
8CH  
-
-
-
-
Read ID (RDID) 10  
00H  
Hi-Z 00H Hi-Z  
Note:  
1. Operation: SIN = Serial In, SOUT = Serial Out, Bus Cycle 1 = Op Code  
2. X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary); cont. = continuous  
3. One bus cycle is eight clock periods.  
4. Sector Earse addresses: use AMS -A12, remaining addresses can be VIL or VIH  
Block Earse addresses: use AMS -A16, remaining addresses can be VIL or VIH  
5. To continue programming to the next sequential address location, enter the 8-bit command, followed by the data to be  
programmed.  
6. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE .  
7. The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE .  
8. The Jedec-Read-ID is output first byte 8CH as manufacture ID; second byte 20H as top memory type; third byte 13H as  
memory capacity.  
9. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each  
other. The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both  
Elite Semiconductor Memory Technology Inc.  
Publication Date: May 2009  
Revision: 0.2 9/34  
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