S1D15E06 Series
Table 10.2.2
[VDD = 2.4V to 3.0V, Ta = –40 to +85°C]
Specified value
Parameter
Signal Symbol
Condition
Unit
Min.
Max.
Address hold time
Address setup time
A0
E
tAH6
tAW6
tWCYC6
tRCYC6
0
0
—
—
ns
System write cycle time
System read cycle time
300
400
—
—
Data setup time
Data hold time
D0 to D7
tDS6
tDH6
30
15
—
—
Access time
Output disable time
tACC6
tOH6
CL=100pF
—
10
120
120
Enable HIGH-pulse width Read
Write
E
E
tEWHR
tEWHW
tEWLR
tEWLW
150
80
—
—
Enable LOW-pulse width Read
Write
150
80
—
—
Table 10.2.3
Parameter
[VDD = 1.7V to 2.4V, Ta = –40 to +85°C]
Specified value
Signal Symbol
Condition
Unit
Min.
Max.
Address hold time
Address setup time
A0
E
tAH6
tAW6
tWCYC6
tRCYC6
0
0
—
—
ns
System write cycle time
System read cycle time
400
600
—
—
Data setup time
Data hold time
D0 to D7
tDS6
tDH6
40
20
—
—
Access time
Output disable time
tACC6
tOH6
CL=100pF
—
10
200
200
Enable HIGH-pulse width Read
Write
E
E
tEWHR
tEWHW
250
100
—
—
Enable LOW-pulse width Read
Write
tEWLR
250
140
—
—
tEWLW
*1 This is in case of making the access by E, setting the CS1 = LOW.
*2 This is in case of making the access by CS1, setting the E = HIGH.
*3 The rise time and the fall time (tr & tf) of the input signals should be set to 15ns or less. When it is necessary to
use the system cycle time at high speed, the rise time and the fall time should be so set to conform
to (tr+tf) ≤ (tCVC6-tEWLW-tEWHW) or (tr+tf) ≤ (tCYC6-tEWLR-tEWHR).
*4 All the timing should basically be set to 20% and 80% of the “VDD”.
*5 tEWLW, tEWLR should be set to the overlapping zone where the CS1 is on the LOW level (CS2 = HIGH level) and
where the E is on the HIGH level.
Rev. 2.1
EPSON
61
EPSON [ EPSON COMPANY ]
