S1D15E06 Series
Table 10.1.2
[VDD = 2.4V to 3.0V, Ta = –40 to +85°C]
Specified value
Parameter
Signal Symbol
Condition
Unit
Min.
Max.
Address hold time
Address setup time
A0
tAH8
tAW8
0
0
—
—
ns
System write cycle time
System read cycle time
WR
RD
tWCYC8
tRCYC8
300
400
—
—
Control LOW-pulse width (Write)
Control LOW-pulse width (Read)
Control HIGH-pulse width (Write)
Control HIGH-pulse width (Read)
WR
RD
WR
RD
tCCLW
tCCLR
tCCHW
tCCHR
80
200
80
—
—
—
—
200
Data setup time
Data hold time
D0 to D7
tDS8
tDH8
30
15
—
—
RD access time
Output disable time
tACC8
tOH8
CL=100pF
—
10
120
120
Table 10.1.3
Parameter
[VDD = 1.7V to 2.4V, Ta = –40 to +85°C]
Specified value
Signal Symbol
Condition
Unit
Min.
Max.
Address hold time
Address setup time
A0
tAH8
tAW8
0
0
—
—
ns
System write cycle time
System read cycle time
WR
RD
tWCYC8
tRCYC8
400
600
—
—
Control LOW-pulse width (Write)
Control LOW-pulse width (Read)
Control HIGH-pulse width (Write)
Control HIGH-pulse width (Read)
WR
RD
WR
RD
tCCLW
tCCLR
tCCHW
tCCHR
100
250
140
250
—
—
—
—
Data setup time
Data hold time
D0 to D7
tDS8
tDH8
40
20
—
—
RD access time
Output disable time
tACC8
tOH8
CL=100pF
—
10
200
200
*1. This is in case of making the access by WR and RD, setting the CS1 = LOW.
*2. This is in case of making the access by CS1, setting the WR, RD = LOW.
*3. Input signal rise and fall time (tr, tf) must not exceed 15 ns. When the system cycle time is used at a high speed,
it is specified by (tr + tf) ≤ (tCYC8 – tCCLW – tCCHW) or (tr + tf) ≤ (tCYC8 – tCCLR – tCCHR).
*4. Timing is entirely specified with reference to 20% or 80% of VDD.
*5. tCCLW and tCCLR are specified in terms of the overlapped period when CS1 is at LOW (CS2 = HIGH) level and
WR and RD are at LOW level.
Rev. 2.1
EPSON
59
EPSON [ EPSON COMPANY ]
