S1D15E06 Series
(4) Display control output timing
CL
(OUT)
t
DFR
FR
F1, F2
CA
t
DF1,F2
t
DCA
Fig. 10.4
Table 10.4.1
Parameter
[VDD = 3.0V to 3.6V, Ta = –40 to +85°C]
Specified value
Unit
Signal Symbol
Condition
Min.
—
Typ.
125
125
125
Max.
312
312
312
FR delay time
F1, F2 delay time
CA delay time
FR
F1, F2 tDF1, tF2
CA tDCA
tDFR
CL = 50pF
ns
ns
ns
—
—
Table 10.4.2
Parameter
[VDD = 2.4V to 3.0V, Ta = –40 to +85°C]
Specified value
Unit
Signal Symbol
Condition
Min.
—
Typ.
150
150
150
Max.
360
360
360
FR delay time
F1, F2 delay time
CA delay time
FR
F1, F2 tDF1, tF2
CA tDCA
tDFR
CL = 50pF
ns
ns
ns
—
—
Table 10.4.3
Parameter
[VDD = 1.7V to 2.4V, Ta = –40 to +85°C]
Specified value
Unit
Signal Symbol
Condition
Min.
—
Typ.
225
225
225
Max.
514
514
514
FR delay time
F1, F2 delay time
CA delay time
FR
F1, F2 tDF1, tF2
CA tDCA
tDFR
CL = 50pF
ns
ns
ns
—
—
*1. Valid only in master operation
*2. Timing is entirely specified with reference to 20% or 80% of VDD.
64
EPSON
Rev. 2.1
EPSON [ EPSON COMPANY ]
