S1D15E06 Series
Table 10.3.2
[VDD = 2.4V to 3.0V, Ta = –40 to +85°C]
Specified value
Parameter
Signal Symbol
Condition
Unit
Min.
Max.
Serial clock period
SCL HIGH pulse width
SCL LOW pulse width
SCL
tSCYC
tSHW
tSLW
125
50
50
—
—
—
ns
Address setup time
Address hold time
A0
SI
tSAS
tSAH
tSDS
tSDH
100
100
—
—
Data setup time
Data hold time
30
30
—
—
CS-SCL time
CS
tCSS
tCSH
100
200
—
—
Table 10.3.3
Parameter
[VDD = 1.7V to 2.4V, Ta = –40 to +85°C]
Specified value
Signal Symbol
Condition
Unit
Min.
Max.
Serial clock period
SCL HIGH pulse width
SCL LOW pulse width
SCL
tSCYC
tSHW
tSLW
154
60
60
—
—
—
ns
Address setup time
Address hold time
A0
SI
tSAS
tSAH
tSDS
tSDH
120
140
—
—
Data setup time
Data hold time
40
40
—
—
CS-SCL time
CS
tCSS
tCSH
120
350
—
—
*1. Input signal rise and fall time (tr, tf) must not exceed 15 ns.
*2. Timing is entirely specified with reference to 20% or 80% of VDD.
Rev. 2.1
EPSON
63
EPSON [ EPSON COMPANY ]
