S1D15E06 Series
• Relationship between oscillation frequency fOSC, display clock frequency fCL and liquid crystal frame fFR
Table 9.8
Item
fCL
Display mode
fFR
Built-in oscillator
circuit used
See p. 24
Binary display
4 gray-scale
(fCL × DUTY)/4
(fCL × DUTY)/8
Built-in oscillator circuit
not used
External input (fCL)
Binary display
4 gray-scale
(fCL × DUTY)/4
(fCL × DUTY)/8
(fFR indicates the cycle of rewriting one screen; it does not indicate FR signal cycle.)
[Asterisked references]
*1.
*2.
Does not guarantee if there is an abrupt voltage variation during MPU access.
For VDD and V3 system operating voltage range, see Fig. 9.5.
Applicable when the external power supply is used.
*3.
A0, D0 to D5, D6(SCL), D7(SI), RD(E), WR(R/W), CS1, CS2, CLS, CL, FR, F1, F2, CA, M/S, C86, P/S, DOF,
RES and TEST pins
*4.
*5.
*6.
*7.
D0 to D7, FR, DOF, CL, F1, F2 and CA pins
A0, RD(E), WR(R/W), CS1, CS2, CLS, M/S, C86, P/S, RES and TEST pins
Applicable when D0 to D5, D6(SCL), D7(S1), CL, FR, DOF, F1, F2 and CA pins have a high impedance.
Indicates the resistance when 0.1V voltage is applied between the output pin SEGn or COMn and each power
supply (V2, V1, VC, MV1, MV2).
RON =0.1V/∆I (where ∆I denotes current when 0.1V is applied when power is on).
For the relationship between oscillation frequency and frame frequency, see Table 9.8. The standard values of
the external input item are recommended ones.
*8.
*9.
The VC voltage regulating circuit should be adjusted within the electronic volume operation range.
*10. Indicates the current consumed by a single IC when display is on. Use the electronic volume for voltage
regulation. Also use the internal oscillator circuit. The current due to LCD panel capacity and wiring capacity
is not included. Applicable when there is access from the MPU.
Rev. 2.1
EPSON
57
EPSON [ EPSON COMPANY ]
